NDLI: Estimating aliasing in CA and LFSR based signature registers

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Estimating aliasing in CA and LFSR based signature registers

Content Provider	IEEE Xplore Digital Library
Author	Miller, D.M. Zhang, S. Pries, W. McLeod, R.D.
Copyright Year	1990
Description	Author affiliation: Dept. of Comput. Sci., Victoria Univ., BC, Canada (Miller, D.M.; Zhang, S.; Pries, W.; McLeod, R.D.)
Abstract	Aliasing estimations for cellular automata (CA) and linear feedback shift registers (LFSR) data compactors are presented. As data compaction is a heavily relied on technique for built-in self-test (BIST) the results should be of practical, as well as theoretical interest. Aliasing estimation techniques for multiple-input data compactors are considered. In particular, exact and approximate computation techniques are developed and discussed for CA and LFSR registers. Aliasing estimates for CA and LFSR structures are provided for the ISCAS-85 benchmark circuits for single stuck-at and single delay faults.<>
Starting Page	157
Ending Page	160
File Size	362616
Page Count	4
File Format	PDF
ISBN	081862079X
DOI	10.1109/ICCD.1990.130189
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-09-17
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Built-in self-test Delay estimation Linear feedback shift registers Test pattern generators Computer science Compaction Benchmark testing Feedback circuits Circuit faults
Content Type	Text
Resource Type	Article

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