NDLI: The design of a 64-bit integer multiplier/divider unit

Content Provider	IEEE Xplore Digital Library
Author	Eisig, D. Rotstain, J. Koren, I.
Copyright Year	1993
Description	Author affiliation: Intel Israel Ltd., Haifa, Israel (Eisig, D.)
Abstract	The highlights of the design of an integer multiplier/divider unit for a 64-b processor are presented. The final design is the result of a compromise between performance, complexity, and transistor count. It is optimized for two specific operations with the same hardware being shared by the remaining operations. Thus, for example, the multiplier can be configured for the execution of several different multiply operations and its hardware is also heavily utilized in division. The divider design is optimized for repetitive division by small numbers, since this is a characteristic of several important applications planned for the processor. For such small divisors, the reciprocal is calculated and stored in a content-addressable memory. The stored reciprocals can then be used to generate quotients through fast multiplication. Simulations of the planned applications show a 20% to 30% performance increase over alternative designs.<>
Starting Page	171
Ending Page	178
File Size	512207
Page Count	8
File Format	PDF
ISBN	0818638621
DOI	10.1109/ARITH.1993.378095
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-06-29
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Hardware Throughput Delay Design optimization Arithmetic Process design Circuits Timing Pipelines
Content Type	Text
Resource Type	Article

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