NDLI: Design and Implementation of an Embedded FPGA Floating Point DSP Block

Content Provider	IEEE Xplore Digital Library
Author	Langhammer, M. Pasca, B.
Copyright Year	2015
Description	Author affiliation: Altera Eur. Technol. Centre, High Wycombe, UK (Langhammer, M.; Pasca, B.)
Abstract	This paper describes the architecture and implementation, from both the standpoint of target applications as well as circuit design, of an FPGA DSP Block that can efficiently support both fixed and single precision (SP) floating-point (FP) arithmetic. Most contemporary FPGAs embed DSP blocks that provide simple multiply-add-based fixed-point arithmetic cores. Current FP arithmetic FPGA solutions make use of these hardened DSP resources, together with embedded memory blocks and soft logic resources, however, larger systems cannot be efficiently implemented due to the routing and soft logic limitations on the devices, resulting in significant area, performance, and power consumption penalties compared to ASIC implementations. In this paper we analyse earlier proposed embedded FP implementations, and show why they are not suitable for a production FPGA. We contrast these against our solution -- a unified DSP Block -- where (a) the SP FP multiplier is overlaid on the fixed point constructs, (b) the SP FP Adder/Subtracter is integrated as a separate unit, and (c) the multiplier and adder can be combined in a way that is both arithmetically useful, but also efficient in terms of FPGA routing density and congestion. In addition, a novel way of seamlessly combining any number of DSP Blocks in a low latency structure will be introduced. We will show that this new approach allows a low cost, low power, and high density FP platform on current production 20nm FPGAs. We also describe a future enhancement of the DSP block that can support subnormal numbers.
Starting Page	26
Ending Page	33
File Size	228826
Page Count	8
File Format	PDF
ISSN	10636889
e-ISBN	9781479986644
DOI	10.1109/ARITH.2015.18
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-06-22
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Adders Digital signal processing Field programmable gate arrays Registers Routing Pipelines Multiplexing subnormal FPGA floating-point single precision DSP CPA
Content Type	Text
Resource Type	Article

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