NDLI: A New Binary Floating-Point Division Algorithm and Its Software Implementation on the ST231 Processor

Content Provider	IEEE Xplore Digital Library
Author	Jeannerod, C.-P. Knochel, H. Monat, C. Revy, G. Villard, G.
Copyright Year	2009
Abstract	This paper deals with the design and implementation of low latency software for binary floating-point division with correct rounding to nearest.The approach we present here targets a VLIW integer processor of the ST200 family, and is based on fast and accurate programs for evaluating some particular bivariate polynomials. We start by giving approximation and evaluation error conditions that are sufficient to ensure correct rounding. Then we describe the heuristics used to generate such evaluation programs, as well as those used to automatically validate their accuracy.Finally, we propose, for the binary32 format, a complete C implementation of the resulting division algorithm. With the ST200 compiler and compared to previous implementations, the speed-up observed with our approach is by a factor of almost 1.8.
Starting Page	95
Ending Page	103
File Size	353888
Page Count	9
File Format	PDF
ISBN	9780769536705
ISSN	10636889
DOI	10.1109/ARITH.2009.19
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-06-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Software algorithms Delay Polynomials VLIW Error correction Digital arithmetic Algorithm design and analysis Application software Floating-point arithmetic Parallel algorithms VLIW integer processor binary floating-point division correct rounding polynomial evaluation code generation and validation
Content Type	Text
Resource Type	Article

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