NDLI: Multilayer perceptrons on Splash 2

Content Provider	IEEE Xplore Digital Library
Author	Ratha, N.K. Jain, A.K.
Copyright Year	1997
Description	Author affiliation: Exploratory Comput. Vision Group, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA (Ratha, N.K.)
Abstract	Multilayer perceptrons (MLPs) are one of the most popular neural network models for solving pattern classification and image classification problems. Because of their ability to learn complex decision boundaries, MLPs are used in many practical computer vision applications involving classification (or supervised segmentation). Once the connection weights in a MLP have been learnt, the network can be used repeatedly for classification of new input patterns. Several special-purpose architectures have been described in the literature for neural networks as they are slow on a conventional uniprocessor. In this paper, we describe mapping of MLPs onto Splash 2-a "custom computing machine". The main features of the proposed mapping are: (i) the number of nodes in a layer is not fixed; (ii) the number of layers in the network is not fixed; (iii) it is based on a set of reprogrammable FPGAs and a programmable crossbar; and (iv) it has a significant speedup over a uniprocessor. The mapping has been used for implementing a 3-layer MLP for page segmentation application with an appreciable speedup of approximately 150 over a SPARCstation 20 for one million pattern vectors with 20 features per pattern.
Starting Page	138
Ending Page	142
File Size	649947
Page Count	5
File Format	PDF
ISBN	0818679875
DOI	10.1109/CAMP.1997.631926
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-10-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multilayer perceptrons Neural networks Multi-layer neural network Pattern classification Image classification Computer vision Application software Image segmentation Computer architecture Field programmable gate arrays
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Artificial neural network on a SIMD architecture

Pulse mode multilayer neural network based on floating point number representation

Feasibility of Image Compression in FPGA based Neural Networks

FPGA implementation of a multilayer perceptron neural network using VHDL

NeuroFPGA-implementing artificial neural networks on programmable logic devices

Incremental communication for multilayer neural networks in a field programmable gate array

Synthesis of embedded systemC design: a case study of digital neural networks

Real-Time Neural Network Inversion on the SRC-6e Reconfigurable Computer

Multilayer Perceptron Neural Network Architecture using VHDL with Combinational Logic Sigmoid Function

Multilayer perceptrons on Splash 2

Similar Documents

Artificial neural network on a SIMD architecture

Pulse mode multilayer neural network based on floating point number representation

Feasibility of Image Compression in FPGA based Neural Networks

FPGA implementation of a multilayer perceptron neural network using VHDL

NeuroFPGA-implementing artificial neural networks on programmable logic devices

Incremental communication for multilayer neural networks in a field programmable gate array

Synthesis of embedded systemC design: a case study of digital neural networks

Real-Time Neural Network Inversion on the SRC-6e Reconfigurable Computer

Multilayer Perceptron Neural Network Architecture using VHDL with Combinational Logic Sigmoid Function

Multilayer perceptrons on Splash 2