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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Deb, A. Ling, N. |
| Copyright Year | 1993 |
| Description | Author affiliation: Synopsys, Inc., Mountain View, CA, USA (Deb, A.) |
| Abstract | The authors take a holistic approach to developing a system level architecture for the problem of image capture and understanding in binary images. It includes a direct method of image capture that removes many of the I/O bottlenecks inherent in other systems. It also cooperates with an adaptive focusing mechanism in order to be able to provide quickly and efficiently a higher resolution image for a sub-area of the total scene whenever foveal attention is required, which would need considerable overhead in most systems thereby precluding real-time behavior. The architecture supports all the three levels of vision processing (low, intermediate, and high) for real time object recognition in binary images by providing parallel mesh connected simple processors (PEs) for low level processing as well as a hierarchy of successively powerful PEs providing a pyramidal type of structure for higher levels of processing. It is also shown that this can be efficiently implemented as a dense and regular single or multiple VLSI chips making possible direct mounting of the system inside a camera. On the processor (PE) level the authors have added enhancements over previous architectures that make it possible to form a fast and economical image understanding system for all three levels of processing for binary images. The main contribution has been the generally broad system level approach of active vision to the development of the architecture and the three enhancements to the PEs which include a switchbox mechanism for extending the local connectivity to establish communications between nonlocal neighbors, a hardware implementation of an artificial neural network that provides direct support for connectionist processing, and an embedded multilevel pyramid with successively powerful PEs. This is shown to fulfill the processing requirements for real-time binary image understanding applications. |
| Starting Page | 446 |
| Ending Page | 454 |
| File Size | 890075 |
| Page Count | 9 |
| File Format | |
| ISBN | 0818654201 |
| DOI | 10.1109/CAMP.1993.622502 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1993-12-15 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Focusing Image resolution Layout Real time systems Object recognition Very large scale integration Cameras Power generation economics Communication switching Neural network hardware |
| Content Type | Text |
| Resource Type | Article |
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