NDLI: Atomic Vector Operations on Chip Multiprocessors

Content Provider	IEEE Xplore Digital Library
Author	Kumar, S. Daehyun Kim Smelyanskiy, M. Yen-Kuang Chen Chhugani, Jatin Hughes, C.J. Changkyu Kim Lee, V.W. Nguyen, A.D.
Copyright Year	2008
Description	Author affiliation: Microprocessor Technol. Labs., Intel Corp., Santa Clara, CA (Kumar, S.; Daehyun Kim; Smelyanskiy, M.; Yen-Kuang Chen; Jatin Chhugani; Hughes, C.J.; Changkyu Kim; Lee, V.W.; Nguyen, A.D.)
Abstract	The current trend is for processors to deliver dramatic improvements in parallel performance while only modestly improving serial performance. Parallel performance is harvested through vector/SIMD instructions as well as multithreading (through both multithreaded cores and chip multiprocessors). Vector parallelism can be more efficiently supported than multithreading, but is often harder for software to exploit. In particular, code with sparse data access patterns cannot easily utilize the vector/SIMD instructions of mainstream processors. Hardware to scatter and gather sparse data has previously been proposed to enable vector execution for these codes. However, on multithreaded architectures, a number of applications spend significant time on atomic operations (e.g., parallel reductions), which cannot be vectorized using previously proposed schemes. This paper proposes architectural support for atomic vector operations (referred to as GLSC) that addresses this limitation. GLSC extends scatter-gather hardware to support atomic memory operations. Our experiments show that the GLSC provides an average performance improvement on a set of important RMS kernels of 54% for 4-wide SIMD.
Starting Page	441
Ending Page	452
File Size	402634
Page Count	12
File Format	PDF
ISBN	9780769531748
ISSN	10636897
DOI	10.1109/ISCA.2008.38
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-06-21
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Parallel processing Scattering Yarn Computer architecture Multithreading Read-write memory Software performance Microprocessors Application software multiprocessors locks reductions vector SIMD
Content Type	Text
Resource Type	Article

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