NDLI: Instruction Prefetching of Systems Codes with Layout Optimized for Reduced Cache Misses

Content Provider	IEEE Xplore Digital Library
Author	Torrellas, J. Chun Xia
Copyright Year	1996
Abstract	High-performing on-chip instruction caches are crucial to keep fast processors busy. Unfortunately, while on-chip caches are usually successful at intercepting instruction fetches in loop-intensive engineering codes, they are less able to do so in large systems codes. To improve the performance of the latter codes, the compiler can be used to lay out the code in memory for reduced cache conflicts. Interestingly, such an operation leaves the code in a state that can be exploited by a new type of instruction prefetching: guarded sequential prefetching.The idea is that the compiler leaves hints in the code as to how the code was laid out. Then, at run time, the prefetching hardware detects these hints and uses them to prefetch more effectively. This scheme can be implemented very cheaply: one bit encoded in control transfer instructions and a prefetch module that requires minor extensions to existing next-line sequential prefetchers. Furthermore, the scheme can be turned off and on at run time with the toggling of a bit in the TLB. The scheme is evaluated with simulations using complete traces from a 4-processor machine. Overall, for 16-Kbyte primary instruction caches, guarded sequential prefetching removes, on average, 66% of the instruction misses remaining in an operating system with an optimized layout, speeding up the operating system by 10%. Moreover, the scheme is more cost-effective and robust than existing sequential prefetching techniques.
Starting Page	271
Ending Page	271
File Size	1319285
Page Count	1
File Format	PDF
ISBN	0897917863
ISSN	10636897
DOI	10.1109/ISCA.1996.10019
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-05-24
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Prefetching Operating systems Contracts Multimedia databases Research and development Hardware Robustness System-on-a-chip NASA Sun system traces 2-level adaptive prediction branch prediction correlation
Content Type	Text
Resource Type	Article

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