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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Oberoi, P.S. Sohi, G.S. |
| Copyright Year | 2003 |
| Description | Author affiliation: Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA (Oberoi, P.S.; Sohi, G.S.) |
| Abstract | As processor back-ends get more aggressive, front-ends will have to scale as well. Although the back-ends of superscalar processors have continued to become more parallel, the front-ends remain sequential. We describe techniques for fetching and renaming multiple noncontiguous portions of the dynamic instruction stream in parallel using multiple fetch and rename units. It demonstrates that parallel front-ends are a viable alternative to high performance sequential front-ends. Compared with an equivalently sized trace cache, our technique increases cache bandwidth utilization by 17%, front-end throughput by 20%, and performance by 5%. Parallelism also enhances latency tolerance: a parallel front-end loses only 6% performance as the cache size is decreased from 128 KB to 8 KB, compared with a 50-65% performance loss for sequential fetch mechanisms. |
| Sponsorship | IEEE Comput. Soc. Tech. Committee on Comput. Archit. ACM |
| Starting Page | 230 |
| Ending Page | 240 |
| File Size | 357380 |
| Page Count | 11 |
| File Format | |
| ISBN | 0769519458 |
| ISSN | 10636897 |
| DOI | 10.1109/ISCA.2003.1207003 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2003-06-09 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Parallel processing Throughput Pipelines Performance loss Bandwidth Delay Decoding Proposals Computer architecture |
| Content Type | Text |
| Resource Type | Article |
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