Content Provider	IEEE Xplore Digital Library
Author	Yang, L. Watling, J.R. Adam-Lema, F. Asenov, A. Barker, J.R.
Copyright Year	2004
Description	Author affiliation: Dept. of Electron. & Electr. Eng., Glasgow Univ., UK (Yang, L.; Watling, J.R.; Adam-Lema, F.; Asenov, A.; Barker, J.R.)
Abstract	Scaling of Si MOSFETs beyond the 90 nm technology node requires performance boosters in order to sustain the annual increase of intrinsic speed of high-performance (2003). One potential solution is transport enhanced FETs using strained Si channels. High-k dielectrics required to reduce the gate leakage current for equivalent oxide thickness (EOT) are expected to replace SiO/sub 2/ around the 65 nm node in order to enable further scaling. However, achieving high-quality high-k dielectrics on top of Si is problematic (Wilk et al., 2001). Aside from these technological issues, a fundamental drawback of MOSFETs with high-k dielectrics is the mobility degradation due to strong soft optical (SO) phonon scattering (Fischetti et al., 2001). In this work we study the impact of interface roughness and soft optical phonon scattering on the performance of conventional and strained Si n-MOSFETs with high-k dielectrics using a self-consistent ensemble Monte Carlo (EMC) device simulator. The simulated device structures are illustrated.
Starting Page	30
Ending Page	31
File Size	141299
Page Count	2
File Format	PDF
ISBN	0780386493
DOI	10.1109/IWCE.2004.1407303
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFETs Semiconductor device modeling Nanotechnology Dielectric materials Phonons Monte Carlo methods Silicon
Content Type	Text
Resource Type	Article

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