NDLI: Minimization of NAND circuits by rewriting-rules heuristic

Content Provider	IEEE Xplore Digital Library
Author	Goto, K. Tatsumi, H.
Copyright Year	1992
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Kanagawa Inst. of Technol., Japan (Goto, K.; Tatsumi, H.)
Abstract	A method is given for further minimizing the multilevel NAND gate circuit having single-rail inputs obtained by applying the inhibiting-loop method of K. Goto (1989) to the given function. Using several theorems proposed by the authors several rules are used to determine whether the same input exists in the preceding and succeeding gate levels, and to determine whether the common input exists at the same first level of some parallel multilevel NAND gates, or other conditions. The Lisp language program utilizing this method was run on the microVAX-II computer for three-variable P-equivalence classes and four-variable functions. As a result, the coincidences for the three-variable functions and four-variable functions between the ideal results and the obtained results were 40% and 11%, respectively, when using the inhibiting-loop method alone. However, the results improved to 90% and 64%, respectively, by the addition of this reducing method.<>
Starting Page	5
Ending Page	10
File Size	413939
Page Count	6
File Format	PDF
ISBN	0818627603
DOI	10.1109/CMPEUR.1992.218495
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-05-04
Publisher Place	Netherlands
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuits Roentgenium Computer science Cities and towns Humans Minimization methods Application software
Content Type	Text
Resource Type	Article

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