NDLI: A compact design for a highly-parallel shared-memory MIMD computer

Content Provider	IEEE Xplore Digital Library
Author	Kenner, R. Bianchini, R. Dickey, S. Teller, P.J.
Copyright Year	1989
Description	Author affiliation: Courant Inst. of Math. Sci., New York Univ., NY, USA (Kenner, R.; Bianchini, R.; Dickey, S.; Teller, P.J.)
Abstract	The ultracomputer architecture connects hundreds or possibly thousands of processing elements (PEs), each containing a cache but no local memory, to an equal number of memory modules (MMs) via an interconnection network constructed of custom VLSI components that combine (merge) requests from different PEs destined to the same memory location. The network provides a high-bandwidth path from the PEs to MMs, but the memory latency is significantly larger than that encountered in either a uniprocessor or small bus-based multiprocessor. The PE must utilize the high available bandwidth and minimize the effect of network latency. The authors present a design of a 64-PE ultracomputer prototype using AMD AM29000 CPUs, including a description of system packaging using a backplane-free technology. The prototype is expected to be operational in 1990.<>
Starting Page	264
Ending Page	269
File Size	526263
Page Count	6
File Format	PDF
ISBN	0818619090
DOI	10.1109/CMPCON.1989.301939
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1989-02-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Multiprocessor interconnection networks Bandwidth Delay Concurrent computing Computer networks Laboratories Packaging Design engineering Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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