NDLI: PA7300LC integrates cache for cost/performance

Content Provider	IEEE Xplore Digital Library
Author	Hollenbeck, D. Undy, S.R. Johnson, L. Weiss, D. Tobin, P. Carlson, R.
Copyright Year	1996
Description	Author affiliation: Eng. Syst. Lab., Hewlett-Packard Co., Fort Collins, CO, USA (Hollenbeck, D.; Undy, S.R.; Johnson, L.; Weiss, D.; Tobin, P.; Carlson, R.)
Abstract	HP continues its development of low cost, high performance processors with an evolution of the PA7100LC which includes 128 kB of on-chip primary cache. It implements the full PA-RISC1.1 functionality including the little-endian, uncacheable memory, and multimedia extensions of the PA7100LC. The PA7300LC connects directly to an optional second level cache of 256 kB to 64 MB using plug-in cards. It also adds the ability to accelerate I/O stores to certain memory locations for greatly improved graphics performance. The cache system consists of on-chip, 2-way, separate instruction and data caches of 64 kB total each, plus the off-chip second level cache. Memory consists of 8 MB to 3.75 GB of standard DRAMs or SIMMs connecting directly to the processor chip, using either a 72 bit or 144 bit data path. The chip is fabricated in 0.5 micron, 4-level metal CMOS and is designed to run at frequencies up to 160 MHz. The PA7300LC exceeds performance levels of previous generation high-end workstations while lowering overall system cost and power consumption.
Starting Page	167
Ending Page	174
File Size	927632
Page Count	8
File Format	PDF
ISBN	0818674148
ISSN	10636390
DOI	10.1109/CMPCON.1996.501764
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-02-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System-on-a-chip Frequency Workstations Energy consumption Cost function Circuit testing Systems engineering and theory Acceleration Joining processes Power generation
Content Type	Text
Resource Type	Article
Subject	Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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