NDLI: Early evaluation for phased logic circuits using BDDS and MVL

Content Provider	IEEE Xplore Digital Library
Author	Fazel, K. Thornton, M.A. Reese, R.B.
Copyright Year	2005
Description	Author affiliation: Southern Methodist Univ., Dallas, TX, USA (Fazel, K.; Thornton, M.A.)
Abstract	Phased logic (PL) is a design style for binary-valued asynchronous logic circuits. A performance enhancement known as early evaluation (EE) allows for increased throughput in PL circuits. PL circuits are produced using clocked circuit descriptions as input and then automatically mapping them into PL equivalents while adding optimization features. In the process of adding the EE performance enhancement, a special function known as a "trigger function" is extracted from the partitions. Here, we describe a method for finding candidate trigger functions using BDDs and a technique for combining multiple trigger functions to support a single circuit partition using multiple-valued logic (MVL). Experimental results show that these methods yield better coverage as compared to using a single trigger function.
Starting Page	400
Ending Page	403
File Size	186302
Page Count	4
File Format	PDF
ISBN	0780391950
DOI	10.1109/PACRIM.2005.1517310
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-08-24
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic circuits Data structures Boolean functions Clocks Design methodology Logic design Delay Throughput Libraries Encoding
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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