NDLI: High speed I/O circuit design in multiple voltage domains

Content Provider	IEEE Xplore Digital Library
Author	Jex, J. Griffin, J. Johnson, D.R.
Copyright Year	1999
Description	Author affiliation: Intel Corp., DuPont, WA, USA (Jex, J.)
Abstract	Designing I/O drivers and receivers that must work across multiple voltage domains has several unique circuit-design challenges. One challenge is limitations due to process silicon breakdown voltage. A second disadvantage is the need to transition voltage levels. This is typically done with differential amplifier receivers, special high voltage N or P devices, external pull-ups, or voltage translators. Due to differences in switching levels, matching T/sub CO/ delays though identical receivers in different voltage domains will require additional consideration. Finally, system level simulations of chips crossing multiple voltage domains require 4 terminal devices, non-single global power supply nodes, and must handle multiple process technology files.
Starting Page	424
Ending Page	427
File Size	377300
Page Count	4
File Format	PDF
ISBN	0780355822
DOI	10.1109/PACRIM.1999.799566
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-08-22
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit synthesis Power supplies Low voltage Breakdown voltage Silicon Driver circuits Circuit simulation Dielectric breakdown Differential amplifiers Delay
Content Type	Text
Resource Type	Article

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High speed I/O circuit design in multiple voltage domains