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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jie Chen Sikdar, B. |
| Copyright Year | 2014 |
| Description | Author affiliation: Dept. of Electr., Comput. & Syst. Eng., Rensselaer Polytech. Inst., Troy, NY, USA (Jie Chen; Sikdar, B.) |
| Abstract | Hardware techniques such as dynamic voltage and frequency scaling may be used to reduce the energy consumption of network interfaces and achieve load-proportional energy usage. These techniques slow down the operation of the hardware and thus their power savings come at the cost of increased packet delays. This paper presents a methodology to address the energy-delay tradeoff while achieving load-proportional energy usage in wireless networks. The proposed system uses a pipelined implementation of the functional blocks of the medium access control (MAC) layer. Each functional block has its own job queue and is treated as an individual system with an independent clock. The clock frequency of each functional block is dynamically selected based on the length of its job queue. While the pipelined implementation reduces the MAC layer processing delays, the use of queue-length based frequency scaling provides load-proportional energy usage and enhances the overall stability of the system. The performance of the proposed system has been verified through extensive simulations. |
| Starting Page | 3547 |
| Ending Page | 3552 |
| File Size | 112265 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781479920037 |
| DOI | 10.1109/ICC.2014.6883871 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-06-10 |
| Publisher Place | Australia |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Delays Energy consumption Clocks Network interfaces Pipeline processing Computer architecture Wireless networks |
| Content Type | Text |
| Resource Type | Article |
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