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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jie Liu Weaver, B. Zakharov, Y. White, G. |
| Copyright Year | 2007 |
| Description | Author affiliation: Univ. of York, York (Jie Liu; Weaver, B.; Zakharov, Y.; White, G.) |
| Abstract | The FPGA design of an adaptive antenna array beamformer is presented. The complex-valued array weights are calculated using the MVDR algorithm whose implementation is based on dichotomous coordinate descent (DCD) iterations. The DCD algorithm allows the multiplication-free solution of the normal equations, resulting in an area-efficient FPGA design that requires approximately 400 slices for the DCD core. Antenna beampatterns obtained from weights calculated in the fixed-point FPGA platform are compared with those of a floating-point simulation. The comparison shows good match of the results for linear arrays of as large as 64 elements. For a 64-element array, the proposed design could provide a weight update rate as high as 28 kHz. |
| Starting Page | 2551 |
| Ending Page | 2556 |
| File Size | 373072 |
| Page Count | 6 |
| File Format | |
| ISBN | 1424403537 |
| DOI | 10.1109/ICC.2007.422 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-06-24 |
| Publisher Place | UK |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Field programmable gate arrays Array signal processing Equations Linear antenna arrays Communications Society Adaptive arrays Antenna arrays Receiving antennas Iterative algorithms Direction of arrival estimation |
| Content Type | Text |
| Resource Type | Article |
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