NDLI: Contention resolution using multi-stage fiber delay line buffer in a photonic packet switch

Content Provider	IEEE Xplore Digital Library
Author	Harai, H. Wada, N. Kubota, F. Chujo, W.
Copyright Year	2002
Description	Author affiliation: Commun. Res. Lab., Tokyo, Japan (Harai, H.; Wada, N.; Kubota, F.; Chujo, W.)
Abstract	We focus on contention resolution using an optical fiber delay line (FDL) buffer in a photonic packet switch. A scheduler for contention resolution may not have a high-speed electronic processor, which limits performance of a photonic packet switch. We thus propose a multi-stage buffer based on tree structure. The buffer has multiple schedulers to compensate for the slow processing speed of each scheduler. We show the performance of the multistage buffer with respect to packet loss probability through simulation experiments. As a result, we find that the performance of a multistage buffer is strongly affected by the small number of FDLs in the first stage. We also show the number of FDLs in a multi-stage buffer needed to get the same performance as a high-speed one-stage buffer.
Starting Page	2843
Ending Page	2847
File Size	237525
Page Count	5
File Format	PDF
ISBN	0780374002
DOI	10.1109/ICC.2002.997360
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-04-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay lines Optical buffering Packet switching Optical packet switching Optical switches Processor scheduling Optical fibers High-speed electronics Tree data structures Performance loss
Content Type	Text

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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