NDLI: Performance evaluation of DC-free error-control block codes

Content Provider	IEEE Xplore Digital Library
Author	Fengqin Zhai Yan Xin Fair, I.J.
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta. (Fengqin Zhai; Yan Xin; Fair, I.J.)
Abstract	DC-free error-control block codes integrate dc-free encoding and error-control block encoding. To reduce the effect of error extension introduced by dc-free decoding and to allow for soft decoding of error-control codes, dc-free error-control block codes are decoded at the receiver by applying error-control decoding techniques prior to dc-free decoding. In this paper, we show that in addition to ensuring both dc-free and error-control properties in the encoded symbol sequence, it is possible to use this coding structure to enforce runlength constraints. We also model the dc-constrained channel with a simple RC high-pass filter, and demonstrate that on this channel with additive white Gaussian noise, dc-free error-control block codes result in superior bit error rate performance, particularly when source data logic values are not equiprobable
Starting Page	451
Ending Page	455
File Size	189336
Page Count	5
File Format	PDF
ISBN	0780385497
DOI	10.1109/ICCS.2004.1359417
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-09-07
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Block codes Decoding Computer errors Additive white noise Bit error rate Error correction codes Filters Logic Control systems Frequency domain analysis
Content Type	Text
Resource Type	Article

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