NDLI: Detecting and Eliminating Potential Violations of Sequential Consistency for Concurrent C/C++ Programs

Content Provider	IEEE Xplore Digital Library
Author	Yuelu Duan Xiaobing Feng Lei Wang Chao Zhang Pen-Chung Yew
Copyright Year	2009
Abstract	When a concurrent shared-memory program written with a sequential consistency (SC) model is run on a machine implemented with a relaxed consistency (RC) model, it could cause SC violations that are very hard to debug. To avoid such violations, programmers need to provide explicit synchronizations or insert fence instructions. In this paper, we propose a scheme to detect and eliminate potential SC violations by combining Shasha/Snir's conflict graph and delay set theory with existing data race detection techniques. For each execution, we generate a race graph, which contains the improperly synchronized conflict accesses, called race accesses, and race cycles formed with those accesses. As a race cycle would probably lead to a non-sequential-consistent execution, we call it a potential violation of sequential consistency (PVSC) bug. We then compute the race delays of race cycles, and suggest programmers to insert fences into source code to eliminate PVSC bugs. We further convert a race graph into a PC race graph, and improves cycle detection and race delay computation to O(n^2), where n is the number of race access instructions. We evaluate our approach with the SPLASH-2 benchmarks, two large real-world applications (MySQL and Apache), and several multi-threaded Cilk programs. The results show that (1) the proposed approach could effec-tively detect PVSC bugs in real-world applications with good scalability; (2) it retains most of the performance of the concurrent program after inserting required fence instructions, with less than 6.3% performance loss; and (3) the additional cost of our approach over traditional race detection techniques is quite low, with 3.3% on average.
Starting Page	25
Ending Page	34
File Size	408485
Page Count	10
File Format	PDF
ISBN	9780769535760
DOI	10.1109/CGO.2009.29
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-03-22
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Programming profession Delay Set theory Computer bugs Performance loss Chaos Computer science Laboratories Concurrent computing Computer architecture relaxed memory model Sequential consistency data race detection delay set fence
Content Type	Text
Resource Type	Article

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