NDLI: Design and implementation of an effective HyperTransport core in FPGA

Content Provider	IEEE Xplore Digital Library
Author	Fei Chen Hailiang Cheng Xjiaojun Yang Rui Liu
Copyright Year	2008
Description	Author affiliation: Nat. Res. Center for Intell. Comput. Syst., Chinese Acad. of Sci., Beijing (Fei Chen; Hailiang Cheng; Xjiaojun Yang; Rui Liu)
Abstract	This paper presents a design and implementation of a HyperTransport (HT) core in lattice SCM FPGA which can run at 800 MHz DDR link frequency. An effective approach is also proposed to solve the ordering problem caused by different virtual channels which exists not only in HT but also PCI-e. HT is a high performance, low latency I/O standard which can be used directly to connect with some general-purpose processors, such as AMDpsilas Opteron processor family. HT interface on Opteron processor run at a maximum of 1 GHz frequency. However, most HT core in FPGA runs at a maximum of 500 MHz frequency which limits the performance of communication. In this paper, a 16 bit 800 MHz HT core is proposed to reduce the gap of ASIC and FPGA.
Starting Page	437
Ending Page	443
File Size	913858
Page Count	7
File Format	PDF
ISBN	9781424426393
ISSN	15525244
DOI	10.1109/CLUSTR.2008.4663805
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-09-29
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Clocks Program processors Synchronization Registers Bandwidth Computer architecture
Content Type	Text
Resource Type	Article

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