NDLI: MyVIA: a design and implementation of the high performance Virtual Interface Architecture

Content Provider	IEEE Xplore Digital Library
Author	Yu Chen Xiaoge Wang Zhenqiang Jiao Jun Xie Zhihui Du Sanli Li
Copyright Year	2002
Description	Author affiliation: Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China (Yu Chen; Xiaoge Wang; Zhenqiang Jiao; Jun Xie; Zhihui Du; Sanli Li)
Abstract	Virtual Interface Architecture (VIA) established a communication model with low latency and high bandwidth, and defined the standard of user-level high-performance communication specification in cluster systems. This paper analyzes the current development, principle and implementations of VIA, and presents user-level high-performance communication software, MyVIA, based on Myrinet, which is comfortable with VIA specification. The paper first describes the design principle and framework of MyVIA, then proposes new technologies of MyVIA including User TLB, continued host physical memory and varied NIC buffer, the pipelining communication based on resource and DMA chain, and physical descriptor ring. Experimental results of performance comparisons and analysis are presented; the one-way bandwidth of MyVIA for a 4 KB message is 250 MB/s, and the lowest one-way latency is 8.46 /spl mu/s, which shows that the performance of MyVIA surpassed that of other implementations of VIA.
Sponsorship	IEEE Comput. Soc. Task Force on Cluster Comput. (TFCC)
Starting Page	160
Ending Page	167
File Size	498857
Page Count	8
File Format	PDF
ISBN	0769520669
DOI	10.1109/CLUSTR.2002.1137741
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-09-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Delay Bandwidth Hardware Kernel Application software Performance analysis Operating systems Computer interfaces Linux
Content Type	Text
Resource Type	Article

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