NDLI: Linear Combinations of DVFS-Enabled Processor Frequencies to Modify the Energy-Aware Scheduling Algorithms

Content Provider	IEEE Xplore Digital Library
Author	Rizvandi, N.B. Taheri, J. Zomaya, A.Y. Young Choon Lee
Copyright Year	2010
Abstract	The energy consumption issue in distributed computing systems has become quite critical due to environmental concerns. In response to this, many energy-aware scheduling algorithms have been developed primarily by using the dynamic voltage-frequency scaling (DVFS) capability incorporated in recent commodity processors. The majority of these algorithms involve two passes: schedule generation and slack reclamation. The latter is typically achieved by lowering processor frequency for tasks with slacks. In this paper, we revisit this energy reduction technique from a different perspective and propose a new slack reclamation algorithm which uses a linear combination of the maximum and minimum processor frequencies to decrease energy consumption. This algorithm has been evaluated based on results obtained from experiments with three different sets of task graphs: 1,500 randomly generated task graphs, and 300 task graphs of each of two real-world applications (Gauss-Jordan and LU decomposition). The results show that the amount of energy saved in the proposed algorithm is 13.5%, 25.5% and 0.11% for random, LU decomposition and Gauss-Jordan task graphs, respectively, these percentages for the reference DVFSbased algorithm are 12.4%, 24.6% and 0.1%, respectively.
Starting Page	388
Ending Page	397
File Size	776234
Page Count	10
File Format	PDF
ISBN	9781424469871
e-ISBN	9781424469888
DOI	10.1109/CCGRID.2010.38
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-17
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Frequency Scheduling algorithm Energy consumption Australia Processor scheduling High performance computing Clouds Distributed computing Costs Temperature power consumption Dynamic voltage scaling scheduling
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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