NDLI: High-speed and low-power serial accumulator for serial/parallel multiplier

Content Provider	IEEE Xplore Digital Library
Author	Meher, M.R. Ching-Chuen Jong Chip-Hong Chang
Copyright Year	2008
Description	Author affiliation: Centre for Integrated Circuits & Syst., Nanyang Technol. Univ., Singapore (Meher, M.R.; Ching-Chuen Jong; Chip-Hong Chang)
Abstract	This paper presents a new approach to serial/parallel multiplier design by using parallel 1psilas counters to accumulate the binary partial product bits. The 1psilas in each column of the partial product matrix due to the serially input operands are accumulated using a serial T-flip flop (TFF) counter. Consequently, the column height is reduced from N to $[log_{2}$ N]+1. This logarithmic reduction results in a very small carry save adder (CSA) array or tree required before the two final summands are added up to obtain the final product. The counters can be clocked at very high frequency (around 1.5 GHz as dictated mainly by the TFF propagation delay) and the accumulation frequency is independent of the operand size. The proposed accumulation method achieves 33%, 38%, 43% gain in speed respectively for 31, 63, 127 operands accumulators and on average 42% reduction in power consumption over CSA based accumulation implemented in 0.18 mum CMOS technology.
Starting Page	176
Ending Page	179
File Size	451390
Page Count	4
File Format	PDF
ISBN	9781424423415
e-ISBN	9781424423422
DOI	10.1109/APCCAS.2008.4745989
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-30
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Adders Counting circuits Frequency Energy consumption Propagation delay CMOS technology Digital signal processing chips High speed integrated circuits Design engineering Integrated circuit technology
Content Type	Text
Resource Type	Article

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