NDLI: Real-time deblocking filter for MPEG-4 systems

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Real-time deblocking filter for MPEG-4 systems

Content Provider	IEEE Xplore Digital Library
Author	Hung-Chi Fang Tu-Chih Wang Liang-Gee Chen
Copyright Year	2002
Description	Author affiliation: Graduate Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan (Hung-Chi Fang; Tu-Chih Wang; Liang-Gee Chen)
Abstract	This paper presents a deblocking filter architecture in the MPEG-4 standard. This architecture performs as a 1D nonlinear filter across the block boundary to efficiently suppress blocking artifacts. Two shift register banks are used in the design; their use greatly reduces the control complexity of data flow. Due to efficient scheduling, the size of storage and the total clock cycles are minimized. The maximum processing rate of this architecture mapped in 0.35 /spl mu/m technology is 30 Mpixels/sec, which can support NTSC resolution at 30 frames per second. The power consumption of the design is 46.6 mW while operating frequency is 81 MHz.
Starting Page	541
Ending Page	544
File Size	408637
Page Count	4
File Format	PDF
ISBN	0780376900
DOI	10.1109/APCCAS.2002.1115058
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-10-28
Publisher Place	Indonesia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Real time systems MPEG 4 Standard Low pass filters Filtering Discrete cosine transforms Iterative algorithms Quantization Quadratic programming Digital signal processing Design engineering
Content Type	Text
Resource Type	Article

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