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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Al-Khalili, D. Esonu, M.O. Karlovits, S. |
| Copyright Year | 1991 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., R. Mil. Coll., Kingston, Ont., Canada (Al-Khalili, D.; Esonu, M.O.; Karlovits, S.) |
| Abstract | The effects of different MOS and bipolar device parameters on the switching speed of a BiCMOS buffer are examined. The switching speed is studied for the pull-up situation. Also, an approach to the design of a BiCMOS buffer with high performance is presented. The optimization of the buffer is performed in terms of AT and A-only where A is chip area and AT is switching delay. Results in both cases show that larger transistor sizes are required to drive large loads and to provide faster switching speed. The sizes of the transistors generated using the optimization procedure constitute the optimal buffer for the given design specification. It is also shown that improving the current driving capability of the MOS transistor without improving the bipolar transistor reduces the advantage of the BiCMOS driver over a MOS buffer. The optimization algorithm has been incorporated into a BiCMOS buffer compiler which will allow the automatic generation of a BiCMOS buffer layout.< |
| Starting Page | 1021 |
| Ending Page | 1024 |
| File Size | 458175 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780306201 |
| DOI | 10.1109/MWSCAS.1991.251962 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1992-05-14 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | BiCMOS integrated circuits Logic circuits Delay CMOS technology Integrated circuit technology Design automation Very large scale integration Logic devices Bipolar transistors Military computing |
| Content Type | Text |
| Resource Type | Article |
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