NDLI: Design of a Digital Architecture for Real-Time Video, Enhancement Based on Illuminance-Reflectance Model

Content Provider	IEEE Xplore Digital Library
Author	Ngo, Hau T. Zhang, Ming Z. Li Tao, Asari, Vijayan K.
Copyright Year	2006
Description	Author affiliation: Computational Intelligence and Machine Vision Laboratory, Department of Electrical and Computer Engineering, Old Dominion University, Norfolk, VA 23529. hngox001@odu.edu (Ngo, Hau T.) \|\| Computational Intelligence and Machine Vision Laboratory, Department of Electrical and Computer Engineering, Old Dominion University, Norfolk, VA 23529. vasari@odu.edu (Asari, Vijayan K.) \|\| Computational Intelligence and Machine Vision Laboratory, Department of Electrical and Computer Engineering, Old Dominion University, Norfolk, VA 23529. ltaox001@odu.edu (Li Tao,) \|\| Computational Intelligence and Machine Vision Laboratory, Department of Electrical and Computer Engineering, Old Dominion University, Norfolk, VA 23529. mzhan002@odu.edu (Zhang, Ming Z.)
Abstract	A design of a high performance digital architecture for a nonlinear image enhancement technique is presented in this paper. The image enhancement is based on illuminance-reflectance model which improves the visual quality of digital images and video captured under insufficient or non-uniform lighting conditions [1]. Systolic, pipelined and parallel design techniques are utilized effectively in the proposed FPGA-based architectural design to achieve real-time performance. Estimation and folding techniques are used in the hardware algorithmic design to achieve faster, simpler and more efficient architecture. The video enhancement system is implemented using Xilinx's multimedia development board that contains a VirtexII-X2000 FPGA and it is capable of processing approximately 66 Mega-pixels (Mpixels) per second.
Starting Page	286
Ending Page	290
File Size	3065010
Page Count	5
File Format	PDF
ISBN	1424401720
ISSN	15483746
DOI	10.1109/MWSCAS.2006.382053
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-08-06
Publisher Place	Puerto Rico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Signal processing algorithms Image enhancement Field programmable gate arrays Digital signal processing Computer architecture Image coding Streaming media Parallel processing Reflectivity Algorithm design and analysis
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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