NDLI: Design-for-Test of Mixed-Signal Integrated Circuits

Please wait, while we are loading the content...

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)

2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)

2010 53rd IEEE International Midwest Symposium on Circuits and Systems

2009 52nd IEEE International Midwest Symposium on Circuits and Systems

2008 51st Midwest Symposium on Circuits and Systems

2007 50th Midwest Symposium on Circuits and Systems

2006 49th IEEE International Midwest Symposium on Circuits and Systems

Volume 2 - 2006

Proceedings of the 2006 49th Midwest Symposium on Circuits and Systems

Welcome to the 49th IEEE International Midwest Symposium on Circuits and Systems

Symposium Support

MWSCAS 2006 Advisory Committee

Technical Tracks

MWSCAS 2006 Reviewers

General Information

Student Paper Contest

Myril B. Reed Best Paper Award

Analog in a Digital World

Multicell Delta-Sigma Data Converters

Circuit Techniques for Operational Amplifier Speed and Accuracy Improvement: Analog Circuit Design with Structural Methodology

RF Wireless Integrated Architectures for 4G Communication Systems

Substrate Noise suppression Techniques for Systems on Chip

Advanced Multi-Antenna Techniques

Design-for-Test of Mixed-Signal Integrated Circuits

Sensor Data Fusion and Integration with Applications to Target Tracking and Robotics

Session Program and Abstracts

Table of contents

Chaos Based Random Clock Generator

A Fully Integrated Spread Spectrum Clock Generator Using a Dual-Path Loop Filter

An UHF Passive RFID Transponder Using A Low-Power Clock Generator without Passive Components

A Gigahertz Cyclic Injection DLL Clock Generator with an Infinite Acquisition Range

Table of contents

Leakage Power Reduction in Flip Flops by Using MTCMOS and ULP Switch

A Shared Self-Compacting Buffer for Network-On-Chip Systems

A Digital Adaptive Filter Architecture for Hard-Disk Drive Read Channels

Simultaneous Delay optimization and Depth reduction in Logic trees with minimum resources

Table of contents

Stochastic Mutation Algorithm in Multi-objective Design Optimization

A 9.8-10.7 Gb/s Bang-Bang CDR with Automatic Frequency Acquisition Capability

Analog MIMO detection on the basis of Belief Propagation

The Development of High Efficiency Multijunction Photovoltaic Devices using a Novel Modeling Technique

Table of contents

An Automatic Sizing Tool for Optimal Design of CMOS OTA Based on ACM Model

Ultra low power four-quadrant multiplier/two-quadrant divider circuit using FGMOS

Designing PGAs based on the Current Division Technique

Design of a Four Terminal Floating Nullor based on modified folded-cascode and class AB output stage

Table of contents

A Delay Model for SRAM-Based FPGA Interconnections

Parasitic-Aware and Moment-driven Constraint Satisfying Non-Linear Routing Methodology

Xilinx Virtex-II FPGA Design Acceleration Using a Novel Merging Methodology for Partial Configuration Bitstreams

A dynamic differential reconfiguration circuit for optically differential reconfigurable gate arrays

Table of contents

RF Characteristics of Mica-Z Wireless Sensor Network Motes

A 10 Gb/s Low Swing Receiver for Power Optimization by Accelerated Bit Error Rate Testing

Miniature SAW Device for RF-Wireless Applications Using MEMS Technology

Evaluation of the XMesh Routing Protocol in Wireless Sensor Networks

Table of contents

Early Detection of AZB in H.264 Based on Gaussian Distribution Model

A Low Cost Solution for 2D Memory Access

A Fast Scheme for the Three-Step Search Algorithm by the Utilization of Eight-Bit Partial Sums

A New Architecture for H.264 Variable Block Size Motion Estimation

Contextual approach for oil spill detection in SAR images using image fusion and markov random fields

Efficient Memory Organization and Data Transfer Technique for DWT- EBCOT Integration of JPEG2000

Table of contents

A Lossless Low Voltage Current Sense Amplifier

Instrumentation Amplifier using Robust Rail-to-Rail Operational Amplifiers with gm Control

Power Optimization in Low-Voltage High-Speed High-Resolution Pipelined ADCs

A Systematic Error Model of High-Resolution Pipelined Analog-to-Digital Converters

New Gain Programmable Current Mirrors Based on Current Steering

Table of contents

Algebraic Propositions for Analysis of Linear-Phase FIR Filters

Improved Self Tuned Linear Predictor

Perturbation Analysis of Digital Eigenfilters

Unified Structure to Combat Residuum Echo in Advance Communication Systems

Algorithmic Design of High-Precision Low-Power Multi-Stage Decimation Filters

Nonuniform Discrete Short-Time Fourier Transform A Goertzel Filter Bank versus a FIR Filtering Approach

Table of contents

A 20-Stage CMOS Distributed Amplifier using CMOS Interconnects for Artificial Transmission Lines

Nanoantenna Design for THz-band Rectification

A New 2.4GHz CMOS Low-Noise Amplifier with Automatic Gain Control

An Accurate Sparse-Matrix Semisymbolic Algorithm for Analyzing Distributed Microwave Circuits

Simulation of the Novel Gradually Low-K Dielectric Structure for Crosstalk Reduction in VLSI and Comparison with Low-K Technology

A 4.7-10.5-GHz Ultra-wideband CMOS LNA Using Inductive Inter-stage Bandwidth Enhancement Technique

Table of contents

Bulk CMOS Device Optimization for High-Speed and Ultra-Low Power Operations

Temperature Variation Insensitive Energy Efficient CMOS Circuits in a 65nm CMOS Technology

Yield, Power and Performance Optimization for Low Power Clock Network under Parametric Variations in Nanometer Scale Design

Table of contents

4th-Order Programmable Low-Pass Filter

Novel Cascadable Allpass Filter with a Grounded Capacitor

Component simulation switched-current filters using backward Euler transformation

Automated Design of Multirate Switched-Capacitor Filter Using Constrained Optimization Approach

Table of contents

On-chip Fault-tolerance Utilizing BIST Resources

Dynamic Current Testing for CMOS Domino Circuits

Table of contents

Wireless Interfaces for Implantable Biomedical Microsystems

A Low-Noise Low-Power Preamplifier for Capacitive CMOS-MEMS Gyroscopes

Table of contents

Low-voltage Low-power CMOS IF Programmable Gain Amplifier

A High Efficiency CMOS Class E Power Amplifier

A 5-GHz SiGe RF-Driven Cascode Power Amplifier

A 5 GHz CMOS Variable Gain Low Noise Amplifier for wireless LAN Applications

Table of contents

Conjugate Distributed Arithmetic Adaptive FIR Filters and their Hardware Implementation

Automated Hardware-in-the-Loop Modeling and Simulation in Active Sensor Imaging Using T16713 DSP Units

Roundoff Noise Minimization for a Class of 2-D State-Space Digital Filters Using Separate/Joint Optimization of Error Feedback and Realization

Generalized Data-Aided Equalizers

Table of contents

On the static test of Analogue-to-Digital Converters

Efficient Algorithms For Testing The Two-Level Carry Skip Adder

Stability and Power Consumption Tests for Time Base Selection of an Ocean Bottom Seismometer (OBS)

JHDL Implementation of a BIST Scheme for Testing the Look-Up Tables of SRAM Based FPGAs

Table of contents

Case Study: Hardware Acceleration of the JPEG2000 Kakadu Library

Unsupervised Unmixing of Hyperspectral Imagery

Image Processing in 2-D Array Space with a Minimized Amount of Computation

An Adaptive Low Power Video Line Driver

Table of contents

Cascade Coupling and Support Vector Clustering Based Novel Sorting Method of Radar Pulses

A New Mixed Method for Relative Error Model Order Reduction

System of Interconnected Reconfigurable Linear Threshold Circuits

OPC-Aware Routing Reconstruction for OPE Reduction

Process Variation-Aware Vdd Assignment Technique for Repeated Interconnects

Table of contents

A CMOS 5th Derivative Impulse Generator for an IR-UWB

Silicon Implementation of the SPIHT Algorithm for Compression of ECG Records

A Closed-Form Input Admittance Solution for RF and Microwave Switched Capacitor Arrays

A Novel Level-Shifter Circuit Design For Display Panel Driver

CMOS Integrated Electro-magnetic Force Actuator

Geometric Optimization of Planar Resonator for Wireless Strain Sensing Applications

Table of contents

Design of a 0.18μm Low-Voltage Switched-Current ΣΔ Modulator for Multistandard Communication Systems

A Straightforward Design Methodology for Multi-bit Continuous Time Delta Sigma Modulators

VHF Filtering with Digital Programmability and Accumulation MOS-C

A Differential Approach to Analog Viterbi Decoding

Table of contents

Skew-Tolerant Domino Techniques for High-Speed Baugh-Wooley Multiplier Circuit Design

Truncated Multiplications for the Negative Two's Complement Number System

A Self-Timed 16-bit Multiplier for Low-Power Low-Frequency Applications

Combined Integer and Floating Point Multiplication Architecture(CIFM) for FPGAs and Its Reversible Logic Implementation

Table of contents

Design Tradeoffs in low-power low-voltage transconductors in weak inversion

An Ultra Low Power Low Noise Chopper Amplifier for Wireless BEG

A Versatile Low-voltage CMOS Pseudo-Differential Transconductor with Improved Linearity

A Very Low-Power Class AB/AB Op-amp based Sigma-Delta Modulator for Biomedical Applications

Table of contents

High-Performance Blind Carrier Frequency Offset Estimator for OFDM Systems

Prediction of channel information in multi-user OFDM systems

Third Order Non Linear Distortion from Modulated Blockers in WCDMA Receivers

Student Developed Meteorological Radar Network for Western Puerto Rico

Table of contents

A Novel Delay Model of CMOS VLSI Circuits

A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment

A practical algorithm for connectivity extraction for very large VLSI layouts

Hardware Design and Prototype of an Optical Packet-Switched Ring Network Node

Table of contents

A Study on Voltage Reference Buffers for Low Voltage Switched Capacitor Data Converters

On-Chip Voltage Regulator Protecting Against Power Analysis Attacks

A Low Power Low Voltage Rectifier Circuit

Sub-1V Supply Bandgap Voltage References Based on Asymmetric Differential Pair

Table of contents

Unified Structure to Combat Residuum Echo in Advance Communication Systems

Design of a High Performance Digital Architecture for Real-Time Correction of Radial Lens Distortion

PBuf: An On-Chip Packet Transfer Engine for MONARCH

A Robust High-Speed Chaos-Based Truly Random Number Generator for Embedded Cryptosystems

Table of contents

Three Bio-Inspired Approaches to Telecommunications Defect-Tracking and Reliability-Estimation

A Sensory Learning Scheme for Adaptable Mobile Agents

Polymorphic Architecture for an Electronic Nose (eNose)

Designing a Genetic Algorithm for Function Approximation for Embedded and ASIC Applications

Table of contents

An Experimental Study of Phase Noise in CMOS Phase-Locked Loops Considering Different Noise Sources

A Low Power 440-MHz Pulse-Swallow-Divider Combination Synchronization-Asynchronism-Hybrid Frequency Divider

A Novel Design Method for Phase-Locked Loops of any Order and Type

An Area-Efficient CMOS Current-Mode Phase-Locked Loop

Table of contents

Statistical Property and Subclass Structure of Sequence Triple Code Space for Repeated Placements

Power optimization of Sequential Circuits by Retiming and Rewiring

Functionally-aware Partitioning of Discrete Signal Transforms for Distributed Hardware Architectures

Interconnect-Centric High Level Synthesis for Enhanced Layouts with Reduced Wire Length

Table of contents

An Energy-Based Dual Image Watermarking Technique with Application to Color Images

Parallel Implementation of an Inversion Model for Hyperspectral Remote Sensing

Classification of Underwater Color Images with Applications in the Study of Deep Coral Reefs

A Neural Network CMOS Circuit Implementation for Real-Time Halftoning Applications

Table of contents

Using Padé Approximants to Calibrate a Sensor

A Multipass Spatial and Temporal Image Filtering APS CMOS Image Sensor

RF-Powered Wireless Sensor Circuits for Temperature Monitoring

Table of contents

A Built-in-Test-based Reconfiguration Scheme for Wireless Systems for Increased Quality of Service (QoS)

On-Chip Analog Sinewave Generator with Reduced Circuitry Resources

Strategic Test Cost Reduction with On-Chip Measurement Circuitry for RF Transceiver Front-Ends - An Overview

Low Cost RF Signal Generation for BIST

Table of contents

Implementation and Analysis of Power Consumption for a Power Optimized Decimator Designed for Cascaded Sigma-Delta A/D Converters

ΣΔ ADC Design Considerations for an UMTS Receiver

State space approach to design of continuous time sigma delta ADC with delay in feedback path

A 3.8 Gs/s, 75mW, 10 bit continuous time bandpass ΣΔ ADC in 0.25 μm SiGe BiCMOS technology

Table of contents

Complex Baseband Predistorters for Nonlinear Wideband RF Power Amplifiers

Parasitic Effects on Harmonic Reflection in Active Microwave Frequency Triplers

A 1.5-V 5 GHz CMOS Down-conversion mixer for wireless LAN Applications

Phase Shifter System Using Vector Modulation For Phased Array Radar Applications

Table of contents

Interconnect-Driven Nanoelectronic Circuits

An Algorithm for I/O Pins Partitioning Targeting 3D VLSI Integrated Circuits

Reference-Based Clock Distribution Architectures

Behavioral Modeling of Switched Capacitor Integrators with Application to ΣΔ Modulators

Volume 1 - 2006

48th Midwest Symposium on Circuits and Systems, 2005.

The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.

2003 46th Midwest Symposium on Circuits and Systems

The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002.

Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)

Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)

42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356)

1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)

Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg

Proceedings of the 39th Midwest Symposium on Circuits and Systems

38th Midwest Symposium on Circuits and Systems. Proceedings

Proceedings of 1994 37th Midwest Symposium on Circuits and Systems

Proceedings of 36th Midwest Symposium on Circuits and Systems

[1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems

[1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems

Proceedings of the 33rd Midwest Symposium on Circuits and Systems

Proceedings of the 32nd Midwest Symposium on Circuits and Systems,

Design-for-Test of Mixed-Signal Integrated Circuits

Content Provider	IEEE Xplore Digital Library
Author	Rueda, Adoracion Huertas, Jose L.
Copyright Year	2006
Description	Author affiliation: Director, Institute of Microelectronics at Seville (IMSE); National Microelectronics Center (CNM-CSIC). (Huertas, Jose L.) \|\| Researcher, Department of Analog Design, National Microelectronics Center (CNM-CSIC); Institute of Microelectronics at Seville (IMSE). (Rueda, Adoracion) What to test and what does test need for a complex mixed-signal ASIC are the two main issues this tutorial will try to focus. It will account for several factors: Stimuli generation. An efficient test procedure would use a single signal especially a signal that is easily supplied to a selected input or generated on-chip. Sufficient access. It is preferable to have access to several internal nodes that the tester can read either sequentially or in parallel. Such access permits selection of convenient test points. Single test output. The output should contain all the information required to interpret test signals. Having the information digitally encoded would also reduce tester requirements. Simple measurement set. This set must contain sufficient information about the circuit under test's operational status. System-level decomposition. An efficient test procedure will employ a system-level strategy for decomposing the ASIC into meaningful parts. This decomposition permits testing of each part using a common procedure. These issues are worth attention for specific circuit classes, since there is no universal method valid for any kind of analog and/or mixed-signal function. These factors and their application for solving testing problems in general or for specific circuits will be presented and discussed. In particular, during the presentations making part of this tutorial, more attention will be paid to integrated filters (Switched-Capacitor and continuous-time), integrated A/D and D/A converters, and PLLs.
File Size	102377
File Format	PDF
ISBN	1424401720
ISSN	15483746
DOI	10.1109/MWSCAS.2006.382189
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-08-06
Publisher Place	Puerto Rico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design for testability Mixed analog digital integrated circuits Circuit testing Microelectronics Integrated circuit testing Biographies USA Councils Transceivers Application specific integrated circuits Digital integrated circuits
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in