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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Goel, S. Gollamudi, S. Kumar, A. Bayoumi, M. |
| Copyright Year | 2004 |
| Description | Author affiliation: Adv. Comput. Studies Center, Louisiana Univ., Lafayette, LA, USA (Goel, S.; Gollamudi, S.; Kumar, A.; Bayoumi, M.) |
| Abstract | We present several designs for 1-bit full adder cell featuring hybrid CMOS logic style. These designs are based on a novel XOR-XNOR circuit that simultaneously produces XOR and XNOR full-swing outputs and outperforms its best counterpart showing 39% improvement in PDP. The new full-adder designs are also categorized in three main categories depending upon the implementation of the logic expression for sum and carry outputs. The results show that all the proposed designs prove to be energy-efficient and outperform several standard full-adder designs. All the designs are able to operate at low voltages without significant loss in signal integrity. The improvement in terms of PDP obtained by the best full-adder cell as compared the best standard design amounts to 24%. |
| File Size | 464840 |
| File Format | |
| ISBN | 078038346X |
| DOI | 10.1109/MWSCAS.2004.1354129 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2004-07-25 |
| Publisher Place | Japan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Adders CMOS logic circuits Logic design Low voltage Signal design Silicon Batteries Power system reliability Arithmetic Compressors |
| Content Type | Text |
| Resource Type | Article |
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