NDLI: Implementation of 1.5 V low power two-path decimation filters for communications /spl Delta/-/spl Sigma/ converters

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Implementation of 1.5 V low power two-path decimation filters for communications /spl Delta/-/spl Sigma/ converters

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Implementation of 1.5 V low power two-path decimation filters for communications /spl Delta/-/spl Sigma/ converters

Content Provider	IEEE Xplore Digital Library
Author	Chia-Ming Liu Hutchens, C.
Copyright Year	2002
Description	Author affiliation: Oklahoma State Univ., Stillwater, OK, USA (Chia-Ming Liu; Hutchens, C.)
Abstract	This paper reports on the fabrication of a low power decimation filter with a two-path architecture. The filter reduces the power consumption by better than 50% over previous work. Instead of decimating data after filtering, the reported technique takes advantage of binary coefficients and performs data division before filtering. Based on the two-path architecture, the adder clock rate as well as the number of additions is reduced. As a result, overall power efficiency is increased by a factor of better than two. Power is further reduced by implementing the design on Silicon-On-Sapphire (SOS) process with the reduction of drain-to-body capacitors. The presented two-path filter has greater attenuation and a narrower transition band than an equivalent implementation of a Sinc filter although with somewhat greater complexity. The selected approach of FIR architecture with its linear phase and excellent delay power product is well suited for communications /spl Delta/-/spl Sigma/ ADCs. The 64 times decimation filter was implemented in Peregrine SOS with a 4-bit input and an 18-bit output data width. The filter was functionally tested and operational up to 23 MHz or 0.36 Msps with a power dissipation of 8.3n W/Hz. Powered at 1.5 V and operating at 10 Msps, the filter consumes 1.5 /spl mu/W at standby and 85 mW at operation.
Sponsorship	IEEE Circuits & Syst. Soc. School of Electr. & Comput. Eng. at Oklahoma State Univ
File Size	206959
File Format	PDF
ISBN	0780375238
DOI	10.1109/MWSCAS.2002.1187173
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-08-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power filters Finite impulse response filter Filtering Fabrication Energy consumption Clocks Capacitors Attenuation Delay Testing
Content Type	Text
Resource Type	Article

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