NDLI: A frequency hopping synthesizer chip for GSM and DCS systems

Content Provider	IEEE Xplore Digital Library
Author	Hakkinen, J. Rahkonen, T. Kostamovaara, J.
Copyright Year	1999
Description	Author affiliation: Dept. of Electr. Eng., Oulu Univ., Finland (Hakkinen, J.)
Abstract	A versatile synthesizer chip capable of operating with an input signal of 2 GHz and a reference signal of 20 MHz was designed in AMS' 12 GHz 0.8 /spl mu/m BiCMOS process. The circuit includes the basic building blocks of a complete PLL-based synthesizer except for the VCO and the loop filter. Thus, the chip has an internal dual modulus prescaler operating in 8/9 or 16/17 mode, a VCO bit M counter, a VCO bit pulse swallow counter, a VCO bit reference counter, a phase-frequency detector and a lock-detector, all of which are programmed with external serial data. The level of the PFD output can be programmed digitally from 0.5 mA to 5.0 mA. Measurement results for a complete synthesizer board with reference signal frequency f/sub ref/=20 MHz, a loop filter and a hybrid VCO running at f/sub ref/=1.060 GHz, for example, are: the settling time of a 20 MHz frequency step /spl Delta/t=14 /spl mu/s, the output power P/sub out/=+9.7 dBm, the level of the 1/sup st/ reference spur is from -84 dBc to -64 dBc depending on the magnitude of the output current pulse of the PFD. The PLL chip consumes about 250 mA from a 5.0 V supply.
Starting Page	356
Ending Page	359
File Size	42879
Page Count	4
File Format	PDF
ISBN	0818689145
DOI	10.1109/MWSCAS.1998.759505
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-08-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Frequency synthesizers GSM Distributed control Voltage-controlled oscillators Phase frequency detector Counting circuits Signal processing Filters Pulse measurements Signal design
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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