NDLI: A pipelined architecture to map ATM cells to 622 Mb/s SONET OC-12 payloads

Content Provider	IEEE Xplore Digital Library
Author	Seetharam, S.W. Minden, G.J. Evans, J.B.
Copyright Year	1994
Description	Author affiliation: Telecommun. & Inf. Sci. Lab., Kansas Univ., Lawrence, KS, USA (Seetharam, S.W.; Minden, G.J.; Evans, J.B.)
Abstract	The Synchronous Optical Network (SONET) and Synchronous Digital Hierarchy (SDH) form a high speed data transmission standard used to transport various types of payloads. Asynchronous Transport Mode (ATM) cells are an increasingly important payload type. This paper describes two pipelined implementations of these mapping functions. The first implementation maps a stream of ATM cells into a SONET OC-12 synchronous payload envelope (SPE). The second circuit maps distinct ATM cell streams into four SONET OC-3c SPE's, which in turn can form a SONET OC-12 signal. Both of these implementations operate at 622 Mb/s. They have been implemented on a single, Xilinx XC3195 Field Programmable Gate Array (FPGA) and have an identical physical interface. This design is part of a system line card that can transmit and receive in the above mentioned modes.<>
Starting Page	245
Ending Page	248
File Size	486030
Page Count	4
File Format	PDF
ISBN	078031915X
DOI	10.1109/ISCAS.1994.409154
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-05-30
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	SONET Payloads Asynchronous transfer mode Synchronous digital hierarchy Data communication Circuits Field programmable gate arrays Bandwidth Switches Computer architecture
Content Type	Text

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