NDLI: An overall FIR filter optimization tool for high granularity implementation technologies

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2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)

Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)

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1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96

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Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94

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EDLICS: a new relaxation-based electrical circuit simulation technique

Relaxation-based steady-state analysis of single- and multi-conductor transmission lines in frequency domain

Mixed mode circuit simulator SPLIT2.1 using dynamic network separation and selective trace

Inverter-based models for current analysis of CMOS logic circuits

Electro-thermal analysis of IC's

Hierarchical techniques for symbolic analysis of large electronic circuits

Symbolic analysis of large analog integrated circuits by approximation during expression generation

Direct hierarchical symbolic transient analysis of linear circuits

An approach to integrated numerical and symbolic circuit analysis

Time-zone: a new algorithm for register allocation in data path synthesis

Storage allocation strategies for data path synthesis of ASICs

Multiport memory based data path allocation focusing on interconnection optimization

Allocation of multiport memories in ASIC data path synthesis

DSP system synthesis including variable data path width

A unified algorithm for estimation and scheduling in data path synthesis

ASAP: a transistor sizing tool for speed, area, and power optimization of static CMOS circuits

High level synthesis with testability constraints

Why cellular automata are better than LFSRs as built-in self-test generators for sequential-type faults

A method of representative fault selection in digital circuits for ATPG

A new strategy for test pattern generation in sequential circuits

Two-dimensional sequential arrays: design for testability approaches

A super fast and memory efficient diagnostic simulation algorithm for combinational circuits

A redefinable symbolic simulation technique to testability design rules checking

Oscillation fault diagnosis for analog circuits based on boundary search with perturbation model

Optimal placement of heat dissipating elements [ hybrid power circuits ]

Integration system as adaptive control system

Region definition for minimizing the number of switchboxes and ordering assignment

Approximate computation of signal characteristics of on-chip RC interconnect trees

Routing a multi-terminal critical net: Steiner tree construction in the presence of obstacles

Automated placement for a leaf cell generator

Statistical characterization and modeling of analog functional blocks

Stochastic interpolation model scheme for statistical circuit design

The Huber concept in device modeling, circuit diagnosis and design centering

Statistical constrained optimization of analog MOS circuits using empirical performance models

Application of the piecewise ellipsoidal approximation technique to design centering

VAMP: a hierarchical framework for design for manufacturability

A CAD environment for performance and yield driven circuit design employing electromagnetic field simulators

IC variability minimization using a new C/sub p/ and C/sub pk/ based variability/performance measure

Worst case design of digital integrated circuits

A floorplanner driven by structural and timing constraints

A new approach to floorplan area optimization: to slice or not to slice?

A floorplanning method with topological constraint manipulation

Interior point methods for placement

The dynamic locking heuristic-a new graph partitioning algorithm

Fuzzy partitioning applied to VLSI-floorplanning and placement

A stochastic reward and punishment neural network algorithm for circuit bipartitioning

A new approach of fractal-dimension based module clustering for VLSI layout

Automatic functional cell generation in the sea-of-gates layout style

A maximum clique derivation algorithm for simplification of incompletely specified machines

Efficient algorithms for the calculation of arithmetic spectrum from OBDD and synthesis of OBDD from arithmetic spectrum for incompletely specified Boolean functions

CUPLAND-a behavioral level description compiler for designing of PLD/EPLD-based systems

Scheduling of signal transition graphs under timing constraints

FPGA-memory tradeoff in the high-level synthesis of FPGA-based reconfigurable systems

A linear time algorithm for timing directed circuit optimizations

Exploring delay/area trade-offs of an LDI filter using a natural based algorithm

Design of optimum totally-perfect connection-blocks of FPGA

A systolic graph partitioning algorithm for VLSI design

Synthesis of customised hardware from ADA

NEAT: an object oriented high-level synthesis interface

Output-column folding for cellular-architecture FPGAs

An improved algorithm for Boolean factoring

Modeling cell processing hardware with action diagrams

Estimating performance characteristics of loop transformations

Computer formulation of averaged models for periodically-switched networks

Graphical specification methods for digital telecommunication ASICs

A novel method for discrete coefficient FIR digital filter design

An overall FIR filter optimization tool for high granularity implementation technologies

Mixed analog-digital simulation: the tools are here...is anyone really using them?

Fast spectrum computation for logic functions using binary decision diagrams

Using binary decision diagrams to speed up the test pattern generation of behavioral circuit descriptions written in hardware description languages

Retiming and clock skew for synchronous systems

Detecting symmetric variables in Boolean functions using generalized Reed-Muller forms

A synthesis framework based on trace and automata theory

Improved lower bounds for the scheduling optimization problem

Detecting hard faults with combined approximate forward/backward symbolic techniques

Efficient and robust test generation-based timing analysis

Direct synthesis of efficient speed-independent circuits from deterministic signal transition graphs

An analog MOS model for circuit simulation and benchmark test results

Modeling symmetry in analog electronic circuits

GOPDE: global optimization in small signal device model parameter extraction

On the modelling of a CMOS magnetic sensor

A VDMOS transistor model taking into account the thermoelectrical interactions

Behavioural modelling of mixed signal ASICs: A new multi-level approach

An integrated modelling technique for hardware/software systems

A physical charge-based model for the space charge region of abrupt and linear semiconductor junctions

A graph-theoretic approach to clock skew optimization

Iterated timing analysis with dynamic partitioning technique for bipolar transistor circuits

Concurrent switch-level timing simulation based on waveform relaxation

Transient simulation of coupled lossy interconnects by window partitioning technique

Interval finite-difference methods for digital MOS circuits simulation

A multi-mode simulation system for GaAs circuits

A model for MOS effective channel mobility with emphasis in the subthreshold and transition region

Improved delay and current models for estimating maximum currents in CMOS VLSI circuits

A timing model for VLSI CMOS circuits verification and optimization

Hierarchical statistical verification of large full custom CMOS circuits

A systematic search method for obtaining multiple local optimal solutions of nonlinear programming problems

Pleasures, perils and pitfalls of symbolic analysis

Signal integrity analysis and optimization of VLSI interconnects using neural network models

Dynamically-wiresized Elmore-based routing constructions

An hierarchical approach to clock routing in high performance systems

Over-the-cell routing with cell orientations consideration

A high performance general purpose multi-point signal router

Analysis and experiments for a parallel solution to the all pairs shortest path problem

A simultaneous placement and global routing algorithm for FPGAs

PHIroute: A parallel hierarchical sea-of-gates router

An algorithm for the place-and-route problem in the layout of analog circuits

Macromodel simplification using dimensional analysis

Accurate modelling of the non-linear settling behaviour of current memory circuits

Modeling of frequency-dependent hysteresis with SPICE

A novel method for the fault detection of analog integrated circuits

Analog fault diagnosis-A practical approach

Constraint generation and placement for automatic layout design of analog integrated circuits

Towards expandable and generalised analogue design automation

Sensitivity-driven placement of analog modules

A fuzzy-logic based tool for topology selection in analog synthesis

A methodology for automatic generation of data conversion topologies from algorithms

Analog design optimization by means of a Tabu Search approach

Improving AWE accuracy using multipoint Pade approximation

Compact modelling in circuit simulation: the general purpose analyser "OPTIMA 3"

High-level specification of behavioural hardware models with MODES

A novel consistent MOSFET model for CAD application with reduced calculation time

Small-signal analysis of nonideal switched-capacitor circuits

Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94

1993 IEEE International Symposium on Circuits and Systems

[Proceedings] 1992 IEEE International Symposium on Circuits and Systems

1991., IEEE International Sympoisum on Circuits and Systems

IEEE International Symposium on Circuits and Systems

IEEE International Symposium on Circuits and Systems,

1988., IEEE International Symposium on Circuits and Systems

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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