NDLI: A parallel global router for sea-of-gates arrays

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Blind adaptive filtering of unknown speech from unknown noise in a single receiver situation

Micro-statistic LMS filtering

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Design of a 2.7 GHz linear OTA in bipolar transistor-array technology with lateral PNPS

The interaction of system structure, index, and numerical stability in classes of differential/algebraic systems

Homotopy methods for solving decoupled power flow equations

Power system small-disturbance stability analysis using circuit-theoretic techniques

Network theoretic conditions for existence and uniqueness of steady state solutions to electric power circuits

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Dynamic behaviors in two novel autonomous circuits with a physical negative resistor characterized by nonsymmetric function

Chaotic behaviour of distributed nonlinear circuits

Design of piecewise-linear Markov maps generating white chaos: an inverse problem of dynamical systems

Simple algorithms for tracing solution curves

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A parallel global router for sea-of-gates arrays

A performance optimization tool for performance-driven micro-cell generation in sea-of-gates arrays

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Standard cell placement with Dynamic Clouds method

RACHANA: an integrated placement and routing approach to CMOS analog cells

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A parallel global router for sea-of-gates arrays

Content Provider	IEEE Xplore Digital Library
Author	Aoki, T. Murakata, M.
Copyright Year	1992
Description	Author affiliation: Toshiba Corp., Kawasaki, Japan (Aoki, T.; Murakata, M.)
Abstract	The authors present a new parallel global routing algorithm for sea-of-gates arrays and its parallel implementation. In the proposed method, making use of the fact that the number of widely distributed nets is comparatively small. The widely distributed nets are processed on one processor and the local nets are processed based on the RSM (region shifting method) in parallel. The algorithm has been implemented on a distributed environment using many engineering workstations. The experimental results have shown that the proposed method achieved good speedups of up to seven using eight processors. The routing quality is the same as the quality obtained by the sequential global routing method.<>
Starting Page	2997
Ending Page	3000
File Size	309457
Page Count	4
File Format	PDF
ISBN	0780305930
DOI	10.1109/ISCAS.1992.230691
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-05-10
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Routing Workstations Parallel processing Design methodology Circuits Ultra large scale integration Concurrent computing Design automation Application software Hardware
Content Type	Text
Resource Type	Article

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