NDLI: A low-voltage CMOS rail-to-rail operational amplifier using double p-channel differential input pairs

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2015 IEEE International Symposium on Circuits and Systems (ISCAS)

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

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2005 IEEE International Symposium on Circuits and Systems

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

Volume 5 - 2004

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Proceedings of 2004 IEEE International Symposium on Circuits and Systems

Proceedings of 2004 IEEE International Symposium on Circuits and Systems

General Chair's welcome

Technical Program Chair's message

Technical Program Committee

Review Committee

Table of contents

ISCAS 2004 technical program

Digital error correction and calibration of gain non-linearities in a pipelined ADC

A new digital background calibration technique for pipelined ADC

A 1.8V 8-bit 250Msample/s Nyquist-rate CMOS pipelined ADC

Digital background auto-calibration of DAC non-linearity in pipelined ADCs

A 28mW 10b 80MS/s pipelined ADC in 0.13/spl mu/m CMOS

On designing linearly tunable high-Q OTA-C filters with low sensitivity

Exact design of all-MOS log filters

Adaptive log domain filters using floating gate transistors

A fully programmable log-domain bandpass filter using multiple-input translinear elements

6.61MHz to 317MHz nth-order current-mode low-pass and high-pass OTA-only-without-C filter

A CMOS bandgap reference circuit for sub-1-V operation without using extra low-threshold-voltage device

Design and optimization of a high PSRR CMOS bandgap voltage reference

Design of a 1.5-V high-order curvature-compensated CMOS bandgap reference

Towards a sub-1 V CMOS voltage reference

A low-power low-voltage MOSFET-only voltage reference

A background digital self-calibration scheme for pipelined ADCs based on transfer curve estimation

A novel queuing architecture for background calibration of pipeline ADCs

A 12-bit 40MSPS 3.3-V 56-mW pipelined A/D convereter in 0.25-/spl mu/m CMOS [convereter read converter]

A 10-bit, 3.3-V, 60MSample/s, combined radix<2 and 1.5-bit/stage pipelined analog-to-digital converter

A low voltage low power 8-bit folding/interpolating ADC with rail-to-rail input range

Behavioral modelling of RF filters in VHDL-AMS for automated architectural and parametric optimization

A design strategy for area efficient high-order high-Q SC filters

Low active-sensitivity allpole active-RC filters using impedance tapering

Digital tuning of analog bandpass filters based on envelope detection

A programmable bandpass array using floating-gate elements

Design of a SiGe low-noise amplifier for 3.1-10.6 GHz ultra-wideband radio

A feedforward compensated high-linearity differential transconductor for RF applications

A PPM Gaussian pulse generator for ultra-wideband communications

A high IIP3 X-band BiCMOS mixer for radar applications

A 12.5 GHz RF matrix amplifier in 180nm SOI CMOS

Termination of averaging networks in flash ADCs

A statistical background calibration technique for flash analog-to-digital converters

A study of digital decoders in flash analog-to-digital converters

Optimal offset averaging for flash and folding A/D converters

6-bit low power low area frequency modulation based flash ADC

Synthesis of amplifier transfer function using time-domain response

Optimized dynamic translinear implementation of the Gaussian wavelet transform

Method for equalizer design based on time-domain symmetry

Exact synthesis of bandpass responses using an isolated cascade connection of same order lowpass and highpass filters

Mixing domains in signal processing

Phase noise and accuracy in quadrature oscillators

A 2.4 GHz CMOS quadrature LC-oscillator/mixer

Quadrature VCO based on direct second harmonic locking

A wideband LC-VCO with enhanced PSRR for SOC applications

DCS1800/WCDMA adaptive voltage-controlled oscillator

A dynamic analysis of a latched CMOS comparator

Generalizations of adjoint networks technique for RLC interconnects model-order reductions

Synthesis of static multiple input multiple output MITE networks

Information capacity and power efficiency in operational transconductance amplifiers

A power-performance adaptive low voltage analog circuit design using independently controlled double gate CMOS technology

An 89dB low-power CMOS /spl Sigma//spl Delta/ modulator for Bluetooth application

A 0.35/spl mu/m CMOS 17-bit@40kS/s sensor A/D interface based on a programmable-gain cascade 2-1 /spl Sigma//spl Delta/ modulator

A CMOS low-power ADC for DVB-T and DVB-H systems

A 0.5/spl mu/m CMOS programmable discrete-time /spl Delta/-/spl Sigma/ modulator with floating gate elements

A 50-MHz CMOS quadrature charge sampling circuit with 66 dB SFDR

Spectral analysis of signals experiencing nonstationary stochastic time-shifts

Power-conscious design methodology for class-A switched-current wave filters

Low power current rectifiers for large scale current-mode signal processing

An ultra-low power analogue directionality system for digital hearing aids

N/sup TH/ order circular symmetry pattern and hexagonal tesselation: two new layout techniques cancelling nonlinear gradient

Lumped passive circuits for 5GHz embedded test of RF SoCs

A translinear-based RF RMS detector for embedded test

The SRE/SRM approach for spectral testing of AMS circuits

A calibration technique for a high-resolution flash time-to-digital converter

An alternative DFT methodology to test high-resolution /spl Sigma//spl Delta/ modulators

Reactance network shaping a sinusoidal pulse with sinusoidal envelope of finite duration

Active RC networks: what benefit is there in having conjugate real zeros in the second-order transfer function?

Mixed-mode parameter analysis of fully differential circuits

Dynamic modelling of analog integrated filters for the stability study of on-chip automatic tuning loops

Simultaneous realization of Z/sub 21//Z/sub 11/ and Y/sub 21/ of an RC two-port

An on-chip DNL estimation and reconfiguration for improved linearity in current steering DAC

Nonlinear distortion in current-steering D/A-converters due to asymmetrical switching errors

A calibration method for current steering digital to analog converters in continuous time multi-bit sigma delta modulators

Modelling of the impact of the current source output impedance on the SFDR of current-steering CMOS D/A converters

A digital calibration for a 16-bit, 400-MHz current-steering DAC

Hardware implementation of complex reaction-diffusion neural networks using log-domain techniques

Time-based arithmetic using step functions

A bio-physically inspired silicon neuron

A reconfigurable bidirectional active 2 dimensional dendrite model

A family of floating-gate adapting synapses based upon transistor channel models

A new charge pump circuit dealing with gate-oxide reliability issue in low-voltage processes

A process, voltage, and temperature compensated CMOS constant current reference

High-PSR bias circuitry for NTSC sync separation

Design of an ultra-low-power current source

Bias current generators with wide dynamic range

High-precision DAC based on a self-calibrated sub-binary radix converter

Addressing static and dynamic errors in bandpass unit element multibit DAC's

A 1-V 400MS/s 14bit self-calibrated CMOS DAC with enhanced dynamic linearity

A 14-bit, 200 MS/s digital-to-analog converter without trimming

A floating-gate DAC array

On leakage current temperature characterization using sub-pico-ampere circuit techniques

Comparison of quasi-/pseudo-floating gate techniques

A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems

Automatic rapid programming of large arrays of floating-gate elements

On mismatch properties of MOS and resistors calibrated ladder structures

A low voltage CMOS constant current-voltage reference circuit

A low-voltage CMOS low-dropout regulator with enhanced loop response

Low-voltage linear voltage regulator suitable for memories

High-voltage-tolerant power supply in a low-voltage CMOS technology

A CMOS bandgap reference with correction for device-to-device variation

Systematic design of double-sampling /spl Sigma//spl Delta/ ADC's with modified NTF

A cascaded continuous-time /spl Sigma//spl Delta/ modulator with 80 dB dynamic range

Direct RF sampling continuous-time bandpass /spl Delta/-/spl Sigma/ A/D converter design for 3G wireless applications

Feed-forward path and gain-scaling - a swing and distortion reduction scheme for second order sigma-delta modulator

A low-power 10-bit continuous-time CMOS /spl Sigma//spl Delta/ A/D converter

CMOS digitally programmable cell for high frequency amplification and filtering

Quasi-parallel multi-path detection architecture using floating-gate-MOS-based CDMA matched filters

A 0.18 /spl mu/m CMOS SC lowpass filter for Bluetooth channel selection

A tunable duty-cycle-controlled switched-R-MOSFET-C CMOS filter for low-voltage and high-linearity applications

A 50-MHz BiCMOS quadrature charge sampler and complex bandpass SC filter for narrowband applications

New CMOS current-mode amplitude shift keying demodulator (ASKD) dedicated for implantable electronic devices

A fully integrated 0.5-7 Hz CMOS bandpass amplifier

A nano-power tuneable edge-detection circuit

A high speed and low power CMOS current comparator for photon counting systems

VLSI potentiostat for amperometric measurements for electrolytic reactions

Low power implementation of an n-tone /spl Sigma//spl Delta/ converter

Low-voltage sigma-delta modulator topologies for broadband applications

Fast and efficient algorithm to design noise-shaping FIR filters for high-order overload-free stable sigma-delta modulators

Domino free 4-path time-interleaved second order sigma-delta modulator

An RF sub-sampling mixer, PGA and /spl Sigma//spl Delta/ ADC for conversion at 900 MHz

Robust design of high gain amplifiers using dynamical systems and bifurcation theory

Harmonic distortion in three-stage nested-Miller-compensated amplifiers

A high-gain offset-compensated differential amplifier

Single Miller capacitor compensated multistage amplifiers for large capacitive load applications

An improved frequency compensation techinique for low power, low voltage CMOS amplifiers [techinique read technique]

A temperature compensated digitally trimmable on-chip IC oscillator with low voltage inhibit capability

High speed array of oscillator-based truly binary random number generators

A CMOS time amplifier for Femto-second resolution timing measurement

Fault modeling of RF blocks based on noise analysis

Accurate fault detection in switched-capacitor filters using structurally allpass building blocks

Low thermal error sampling comparator for accurate settling measurements

Op-amp swing reduction in sigma-delta modulators

Floating gate comparator with automatic offset manipulation functionality

A novel delta-sigma modulator using resonant-tunneling quantizers

Low kickback noise techniques for CMOS latched comparators

A low distortion and fast settling automatic gain control amplifier in CMOS technology

A CMOS high-speed multistage preamplifier for comparator design

Linearized CMOS OTA using active-error feedforward technique

An analytical model for the slewing behavior of CMOS two-stage operational transconductance amplifiers

A programmable gain amplifier buffer design for video applications

A 1.5 V high-linearity CMOS mixer for 2.4 GHz applications

Fully-integrated DECT/Bluetooth multi-band LNA in 0.18 /spl mu/m CMOS

Low voltage, low power folded-switching mixer with current-reuse in 0.18 /spl mu/m CMOS

A DECT/Bluetooth multi-standard front-end with adaptive image rejection in 0.18 /spl mu/m CMOS

Direct RF sampling mixer with recursive filtering in charge domain

A novel single amplifier architecture for second order noise shaping

A programmable analog-to-digital converter

An improved algorithmic ADC clocking scheme

Analysis and compensation of nonlinearity mismatches in time-interleaved ADC arrays

Multi-step analog-to-digital converters with trapping window

Design of a 1.8 V 4.9 /spl sim/ 5.9 GHz CMOS broadband low noise amplifier with 0.28 dB gain flatness using AMER inductor loads

A low-power DC-7-GHz SOI CMOS distributed amplifier

Bandwidth enhancement of multi-stage amplifiers using active feedback

A novel non-uniform distributed amplifier

A 0.1-12 GHz fully differential CMOS distributed amplifier employing a feedforward distortion cancellation technique

Gain/bandwidth programmable PA control loop for GMS/GPRS quad-band applications

An integrated linear RF power detector

Knowledge- and optimization-based design of RF power amplifiers

Transmitter utilising bandpass delta-sigma modulator and switching mode power amplifier

Intermodulation products in the EER technique applied to class-E amplifiers

A comparison of totally digital ADCs for SOCs

Accurate testing of ADC's spectral performance using imprecise sinusoidal excitations

Use of dynamic element matching in a multi-path sigma-delta modulator

Dynamic element matching techniques for delta-sigma ADCs with large internal quantizers

Decimating SC filter for high speed sigma-delta D/A converters

A fixed transconductance bias technique for CMOS analog integrated circuits

Improvements in biasing and compensation of CMOS opamps

A compensation-based optimization methodology for gain-boosted opamp

A low-voltage CMOS rail-to-rail operational amplifier using double p-channel differential input pairs

A 87 dB, 2.3 GHz, SiGe BiCMOS operational transconductance amplifier

Low-voltage CMOS analog four quadrant multiplier based on flipped voltage followers

Compact CMOS linear transconductor and four-quadrant analogue multiplier

Highly-linear, current-feedback resistive source-degenerated MOS transconductor

Compact tunable CMOS OTA with high linearity

Three-decade programmable fully differential linear OTA

Systematic synthesis method for analogue circuits. Part I. Notation and synthesis toolbox

Systematic synthesis method for analogue circuits. Part II. Active-RC circuit synthesis

Systematic synthesis method for analogue circuits. Part III. All-transistor circuit synthesis

Applications of tree/link partitioning for moment computations of general lumped RLC networks with resistor loops

New relaxation-based circuit simulator based on fast automatic differentiation

Design of class AB output stages using the structural methodology

A novel low-voltage low-power class-AB linear transconductor

A novel family of low-voltage very low power super class AB OTAs with significantly enhanced slew rate and bandwidth

Power efficient fully differential low-voltage two stage class AB/AB op-amp architectures

A pseudo-class-AB telescopic-cascode operational amplifier

Configurable direct-conversion / superheterodyne baseband down-link channel for W-CDMA applications

Realization of an analog current-mode 2D DCT

A bump-circuit-based motion detector using projected-activity histograms

A precise CMOS mismatch model for analog design from weak to strong inversion

Programmable multiple input translinear elements

Effects of noise and jitter on algorithms for bandpass sampling in radio receivers

Performance analysis of sampling switches in voltage and frequency domains using Volterra series

A low power thyristor-based CMOS programmable delay element

Jitter in oscillators with 1/f noise sources

A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop

A duty cycle control circuit for high speed applications

A wide-range and fast-locking clock synthesizer IP based on delay-locked loop

A low-voltage low sensitivity sinusoidal VCO for DPLL realizations

High-speed high-precision analog rank order filter in CMOS technology

A Gm-C bump equalizer for low-voltage low-power applications

Programmable-gain amplifiers based on AC couplings for continuous reception

Highly linear wide tuning range CMOS transconductor operating in moderate inversion

A low voltage CMOS transresistance-based variable gain amplifier

A CMOS dB-linear VGA with pre-distortion compensation for wireless communication applications

Fully differential floating-gate programmable OTAs with novel common-mode feedback

A hierarchy of input stages for current feedback operational amplifiers

High performance current-feedback op-amps

Sensitivity-enhanced OEIC with capacitance multiplier for reduced lower-cutoff frequency

On the second harmonic control requirements in balanced common-emitter BJT low noise amplifier

A current-mode interface cascade on COG(CiCC) for TFT-LCD systems

Switched capacitors: a bridge between analog and digital SP

A variable gain high linearity low power baseband filter for WLAN

Analogue adaptive filters using wave synthesis technique

A 1.5V class A 5/sup th/ order log domain filter in SiGe technology

A fully-differential switched capacitor chopper stabilized high-pass filter (mirrored integrator)

A five-transistor bandpass filter element

Optimum area allocation for resistors and capacitors in continuous-time monolithic filters

A 0.8/spl mu/m CMOS programmable IIR SC filter

Low-power compact G/sub m/-C filters structures

Low-IF complex filter with transconductance networks

Series-parallel association of transistors for the reduction of random offset in non-unity gain current mirrors

An adaptive circuits concept to address mismatch in analog circuits

Optimal distribution of the RF front-end system specifications to the RF front-end circuit blocks

A poor man's BiCMOS using standard CMOS

A novel 5GHz RF power detector

Margin normalization and propagation in analog VLSI

A minimization of the charge injection in switched-current circuits

A simple voltage reference using transistor with ZTC point and PTAT current source

An input-free NMOS V/sub T/ extractor circuit in presence of body effects

A low voltage rail to rail V-I conversion scheme for applications in current mode A/D converters

Testing high resolution ADCs using deterministic dynamic element matching

Parameter optimization of deterministic dynamic element matching DACs for accurate and cost-effective ADC testing

An SoC compatible linearity test approach for precision ADCs using easy-to-generate sinusoidal stimuli

Fast implementation of a linearity test approach for high-resolution ADCs using non-linear ramp signals

A digital tuning algorithm for on-chip resistors

An integrated a-Si TFT demultiplexer for driving gate lines in active-matrix arrays

On-chip calibration technique for delay line based BIST jitter measurement

A single-ended to differential capacitive sensor interface circuit designed in CMOS technology

4/2 PAM serial link transmitter with tunable pre-emphasis

Post-optimization design centering for RF integrated circuits

RF CMOS fully-integrated heterodyne front-end receivers design technique for 5 GHz applications

A low voltage dual gate integrated CMOS mixer for 2.4GHz band applications

Comparison of the image rejection between the passive and the Gilbert mixer

A tunable transmission line phase shifter (TTPS)

A lateral-BJT-biased CMOS voltage-controlled oscillator

A new software tool to model measured RF-data with optimum circuit topology

Novel interdigital microstrip bandpass filter with improved spurious response

RF robustness enhancement through statistical analysis of chip package co-design

Design and analysis of a distributed regenerative frequency divider using distributed mixer

Current mode /spl radic/X-domain Palmo technique cell for programmable analog VLSI

Synthesis of log-domain filter with well-defined operating point

I/Q imbalance of two-path ladder filters

Analog envelop constrained filter with input uncertainty

A 1.8 V CMOS linear transconductor and its application to continuous-time filters

1.2V low-power four-quadrant CMOS transconductance multiplier operating in saturation region

A novel approach to the linearization of the differential transconductors

Design of constant-delay systems based on symmetry of time-domain response

Winner-take-all class AB input stage: a novel concept for low-voltage power-efficient class AB amplifiers

Design of arbitrary-order minimal operational-amplifier BIBO stable Bode-type variable-amplitude active-RC equalizers

A filter free class D audio amplifier with 86% power efficiency

A rational function based predistorter for high power amplifier

A 1V 4.2mW fully integrated 2.5Gb/s CMOS limiting amplifier using folded active inductors

A novel matrix-based lumped-element analysis method for CMOS distributed amplifiers

An IF-sampling timing skew-insensitive parallel S/H circuit

A very low-power CMOS parallel A/D converter for embedded applications

A frequency digitizer based on the continuous time phase domain noise shaping

Programmable voltage-output, floating-gate digital-analog converter

An I/Q-multiplexed and OTA-shared CMOS pipelined ADC with an A-DQS S/H front-end for two-step-channel-select low-IF receiver

Modelling and optimization of low pass continuous-time sigma delta modulators for clock jitter noise reduction

Design issues and performance limitations of a clock jitter insensitive multibit DAC architecture for high-performance low-power CT /spl Sigma//spl Delta/ modulators

Sigma-delta modulators operated in optimization mode

Reducing quantization noise with recursive /spl Sigma//spl Delta/ modulators

Taking advantage of LVDS input buffers to implement sigma-delta A/D converters in FPGAs

A continuous-time field programmable analog array (FPAA) consisting of digitally reconfigurable G/sub M/-cells

Distortion cancellation via polyphase multipath circuits

Log-domain wavelet bases

Chaos in a differential fourth-order log-domain band-pass filter

A novel four quadrant CMOS analog multiplier/divider

A 0.35/spl mu/m current-mode T/H with -81dB THD

A 0.8V CMOS analog decoder for an (8,4,4) extended Hamming code

Low power LVDS transmitter with low common mode variation for 1GB/s-per pin operation

Loop delay compensation in bandpass continuous-time /spl Sigma//spl Delta/ modulators without additional feedback coefficients

A multirate based band-pass sigma-delta modulator

Sigma-delta analog to digital converter architecture based upon a modulator design employing a mirrored integrator

Multibit quadrature sigma-delta modulator with DEM scheme

An IF-sampling SC complex lowpass /spl Sigma//spl Delta/ modulator with high image rejection by capacitor sharing

Low-distortion delta-sigma topologies for MASH architectures

A programmable coefficient continuous-time A/D /spl Delta/-/spl Sigma/ modulator

A 0.8-/spl mu/W switched-capacitor sigma-delta modulator using a class-C inverter

A 4/sup th/ order single-loop delta-sigma ADC with 8-bit two-step flash quantization

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