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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Clapp, M. Etienne-Cummings, R. |
| Copyright Year | 2001 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA (Clapp, M.) |
| Abstract | An imager chip has been designed, fabricated, and tested having two unique pixel types interleaved on the same array. The dual-pixel design enables optimization for two separate tasks. One type of pixel is an Active Pixel Sensor (APS), which is used to produce a low-noise image. The other type is a custom-designed pixel optimized for computing the centroid of a moving object in the scene. The APS array is 120 columns/spl times/36 rows, with a pixel size of 14.7 /spl mu/m/spl times/14.7 /spl mu/m. The centroid array has 60 columns and 36 rows, with a larger pixel size of 29.4 /spl mu/m/spl times/29.4 /spl mu/m. The chip was fabricated using standard scalable rules on a 0.7 /spl mu/m CMOS process, with one polysilicon layer, 3 metal layers, and a linear capacitor layer. APS images were taken at a frame rate of 30 fps, and centroid data was taken at a rate of 180 (x,y) coordinates per second. The chip consumed 3.2 mW. |
| Sponsorship | IEEE Circuits & Syst. Soc |
| Starting Page | 501 |
| Ending Page | 504 |
| File Size | 444961 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780366859 |
| DOI | 10.1109/ISCAS.2001.921357 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2001-05-06 |
| Publisher Place | Australia |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Pixel Image quality CMOS process Image sensors Layout CMOS image sensors Charge coupled devices CMOS technology Circuit noise Switches |
| Content Type | Text |
| Resource Type | Article |
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