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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yen-Tai Lai Chi-Chou Kao Wu-Chien Shieh |
| Copyright Year | 1999 |
| Description | Author affiliation: Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan (Yen-Tai Lai) |
| Abstract | Adjacent wires in a VLSI chip become closer as the fabrication technology rapidly evolves. Accordingly it becomes important to consider crosstalk caused by the coupling capacitance between adjacent wires in the layout design for the fast and safe VLSI circuits. The crosstalk is a function of coupling length and distance. The coupling length can be reduced by segment rearrangement technique. This paper presents a crosstalk minimization technique by adjusting the space between adjacent wires. An example is shown in this paper to demonstrate the effectiveness of the technique. |
| Starting Page | 270 |
| Ending Page | 273 |
| File Size | 315625 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780354710 |
| DOI | 10.1109/ISCAS.1999.780147 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1999-05-30 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Quadratic programming Crosstalk Minimization methods Wires Very large scale integration Coupling circuits Capacitance Routing Integrated circuit interconnections Fabrication |
| Content Type | Text |
| Resource Type | Article |
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