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Content Provider | IEEE Xplore Digital Library |
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Author | Lan-Da Van Shuenn-Shyang Wang Shing Tenqchen Wu-Shiung Feng Bor-Shenn Jeng |
Copyright Year | 1999 |
Description | Author affiliation: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan (Lan-Da Van) |
Abstract | A lower-error and lower-variance n/spl times/n multiplier is suitably proposed for VLSI design. Considering the next lower significant stage in P/sub n-1/ column and a useful error-compensation model in the least significant part, and utilizing a near optimized index to classify the error terms are our strategies in order to achieve lower error and variance as compared with previously proposed structure in the subproduct-array of the Baugh-Wooley algorithm. This novel structure applied to the fixed-width low-pass digital FIR filter for a speech signal processing system has excellent performance in reducing maximum error, average error, and variation of errors. |
Starting Page | 130 |
Ending Page | 133 |
File Size | 298331 |
Page Count | 4 |
File Format | |
ISBN | 0780354710 |
DOI | 10.1109/ISCAS.1999.778802 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 1999-05-30 |
Publisher Place | USA |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Speech processing Signal processing algorithms Digital signal processing Hardware Finite impulse response filter Error compensation Telecommunications Very large scale integration MPEG standards Digital cameras |
Content Type | Text |
Resource Type | Article |
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