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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Sumi, Y. Syoubu, K. Obote, S. Fukui, Y. |
| Copyright Year | 1998 |
| Description | Author affiliation: Tottori Sanyo Electr. Co. Ltd., Japan (Sumi, Y.) |
| Abstract | The lock-up time of a PLL frequency synthesizer depends on each loop gain. In this paper, we pay attention to the gain of a programmable divider which is one of the important elements of PLL, and propose a new method for improving the gain of programmable divider. In order to achieve the increase in gain of the programmable divider, we propose a new PLL frequency synthesizer with multi-programmable divider by which the gain is increased even when the same reference frequency and the same division ratio as usual are used. It will be shown by the theoretical considerations and experimental results that a higher speed lock-up time can be achieved. |
| Starting Page | 425 |
| Ending Page | 428 |
| File Size | 291027 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780344553 |
| DOI | 10.1109/ISCAS.1998.698903 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1998-05-31 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Phase locked loops Frequency synthesizers Detectors Frequency conversion Phase detection Voltage-controlled oscillators Transient response Transfer functions Phase noise Communications technology |
| Content Type | Text |
| Resource Type | Article |
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