NDLI: Efficient memory management techniques to speed up the conventional transient simulation of piecewise linear circuits including power electronics

Content Provider	IEEE Xplore Digital Library
Author	Leelarasmee, E. Hwangkhunnatham, M.
Copyright Year	1997
Description	Author affiliation: Dept. of Electr. Eng., Chulalongkorn Univ., Bangkok, Thailand (Leelarasmee, E.)
Abstract	The transient simulation of piecewise linear circuits, including power electronics, using traditional simulation algorithms is revised by adding a dynamic memory management technique called LU matrix cache. It makes use of free main memory to store past copies of LU factors for future reuse. This technique can be easily added to a general purpose circuit simulator to increase its execution speed significantly when applied to piecewise linear circuits. Furthermore, a matrix partition technique is presented to reduce the storage requirement of multiple LU factors by storing only parts that change from one iteration to another.
Starting Page	941
Ending Page	944
File Size	296574
Page Count	4
File Format	PDF
ISBN	078033583X
DOI	10.1109/ISCAS.1997.621869
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-06-12
Publisher Place	Hong Kong
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Memory management Circuit simulation Power electronics Piecewise linear techniques Diodes Equations Computational modeling Piecewise linear approximation Capacitors Switches
Content Type	Text
Resource Type	Article

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Efficient memory management techniques to speed up the conventional transient simulation of piecewise linear circuits including power electronics