NDLI: Electronic System Level Models for Functional Verification of System-on-Chip

Content Provider	IEEE Xplore Digital Library
Author	Adamov, A. Mostovaya, K. Syzonenko, I. Melnik, A.
Copyright Year	2007
Description	Author affiliation: Dept. of DAD, Kharkov Nat. Univ. of Radio Electron., Kharkov (Adamov, A.; Mostovaya, K.; Syzonenko, I.; Melnik, A.)
Abstract	Modern verification environments based on object-oriented methodology is a system-level solution that manages the process and data for a particular system-on-chip model. These systems give an ability to integrate smaller blocks of design into larger blocks, which may eventually be integrated into a system. That is reason for performing designing and functional verification at a system level, which allow teams to rapidly create large system-on-chip designs by integrating premade blocks. Integrated verification systems used to store and manage huge amount of simulation data. However, when the amount of data is large, it is difficult to analyze and extract information from it. This data can be archived for later use or it can be mined to look for different kind of violations or to get statistical information about the specified design. The paper describes the system-level verification environment for a functional verification system-on-chip models. With the help of novel approach we can easily use opportunities, that system-level modeling gives us, such as: early software validation of the system, performance analysis of the system, transaction-level verification of the project, architectural analysis of system-on-chip (SoC) , power analysis of a chip, searching hardware/software tradeoffs.
Starting Page	348
Ending Page	350
File Size	327760
Page Count	3
File Format	PDF
ISBN	9665335870
DOI	10.1109/CADSM.2007.4297576
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-02-19
Publisher Place	Ukraine
Access Restriction	Subscribed
Rights Holder	Lviv Polytechnic National University
Subject Keyword	System-on-a-chip Object oriented modeling Power system modeling Hardware Data mining Process design Performance analysis Software prototyping Virtual prototyping Software performance knowledge discovery Verification system level modeling System-on-Chip data mining
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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