NDLI: The effect of isolation edge profile on the leakage and breakdown characteristics of advanced bipolar transistors

Content Provider	IEEE Xplore Digital Library
Author	Ratnam, P. Grubisich, M. Mehrotra, B. Iranmanesh, A. Blair, C. Biswal, M.
Copyright Year	1992
Description	Author affiliation: National Semicond., Santa Clara, CA, USA (Ratnam, P.; Grubisich, M.; Mehrotra, B.; Iranmanesh, A.; Blair, C.; Biswal, M.)
Abstract	The authors describe the effect of the isolation edge profile on the leakage and breakdown characteristics of advanced poly emitter NPN bipolar transistors. It is shown that the isolation edge profile can cause considerable base narrowing and reduction of the Gummel number, thus controlling the collector-emitter breakdown voltage, BV/sub ceo/, and the collector-emitter leakage current, I/sub ceo/. The reduction in BV/sub ceo/ can become severe enough so that the devices cannot operate at the maximum supply voltages used in emitter coupled logic (ECL) and BiCMOS circuits. The vertical scaling of the intrinsic device will be constrained under these circumstances to meet the required circuit breakdown characteristics, compromising device parameters such as beta and the unity gain cutoff frequency. Therefore device isolation can control key device parameters, thus becoming a major limiting factor in the development of high-performance bipolar devices.<>
Starting Page	117
Ending Page	120
File Size	481510
Page Count	4
File Format	PDF
ISBN	0780307275
DOI	10.1109/BIPOL.1992.274070
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-10-07
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electric breakdown BiCMOS integrated circuits Isolation technology Impurities Bipolar transistors Leakage current Computer simulation Semiconductor device breakdown Voltage control Performance gain
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Scalable bipolar model for BiCMOS and bipolar circuits

Modeling impact ionization in advanced bipolar transistors for device/circuit simulation

Influence of the Ge profile on VBE and current gain mismatch in Advanced SiGe BICMOS NPN HBT with 200 GHz fT

A poor man's BiCMOS using standard CMOS

Simple technique for improving the hot-carrier reliability of single-poly bipolar transistors

Process simulation high performance bipolar and BiCMOS devices

Design and simulation of BiCMOS opamp

Improved vertical PNP collector-base breakdown using 2D Monte-Carlo TCAD simulations

Effect of narrow-emitter on impurity distribution in polysilicon bipolar transistors

The effect of isolation edge profile on the leakage and breakdown characteristics of advanced bipolar transistors

Similar Documents

Scalable bipolar model for BiCMOS and bipolar circuits

Modeling impact ionization in advanced bipolar transistors for device/circuit simulation

Influence of the Ge profile on VBE and current gain mismatch in Advanced SiGe BICMOS NPN HBT with 200 GHz fT

A poor man's BiCMOS using standard CMOS

Simple technique for improving the hot-carrier reliability of single-poly bipolar transistors

Process simulation high performance bipolar and BiCMOS devices

Design and simulation of BiCMOS opamp

Improved vertical PNP collector-base breakdown using 2D Monte-Carlo TCAD simulations

Effect of narrow-emitter on impurity distribution in polysilicon bipolar transistors

The effect of isolation edge profile on the leakage and breakdown characteristics of advanced bipolar transistors