NDLI: Vertical SiGe-base bipolar transistors on CMOS-compatible SOI substrate

Content Provider	IEEE Xplore Digital Library
Author	Jin Cai Kumar, M. Steigerwalt, M. Ho, H. Schonenberg, K. Stein, K. Huajie Chen Jenkins, K. Qiqing Ouyang Oldiges, P. Tak Ning
Copyright Year	2003
Description	Author affiliation: Res. Div., T.J. Watson Res. Center, Yorktown Heights, NY, USA (Jin Cai)
Abstract	We present a comprehensive study of the DC, RF and circuit performance of vertical SiGe-base npn bipolar transistors on 120nm SOI. It includes the sensitivity of device performance to collector doping N/sub C/, layout, and SOI substrate bias. At large positive substrate bias, measured peak f/sub T/, f/sub MAX/ and ECL ring oscillator speed for nominal 180nm devices are 60GHz, 57GHz and 20psec for N/sub C/=1.5/spl times/10/sup 17//cm/sup 3/ respectively, and 71GHz, 54GHz and 18psec for N/sub C/=4.8/spl times/10/sup 17//cm/sup 3/ respectively. Projected f/sub T/ for a scaled 100nm device on 55nm SOI approaches 200GHz.
Sponsorship	IEEE Electron Devices Soc. Labroatoire d'Archtecture et d'Analyse des Systemes (LAAS)
Starting Page	215
Ending Page	218
File Size	377976
Page Count	4
File Format	PDF
ISBN	0780378008
ISSN	10889299
DOI	10.1109/BIPOL.2003.1274969
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-09-28
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Bipolar transistors Silicon on insulator technology Semiconductor device testing Silicon compounds
Content Type	Text
Resource Type	Article

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