NDLI: Event driven analog modeling for the verification of PLL frequency synthesizers

Content Provider	IEEE Xplore Digital Library
Author	Yifan Wang Van-Meersbergen, C. Groh, H.-W. Heinen, S.
Copyright Year	2009
Description	Author affiliation: Vienna University of Technology (TU Wien), Austria (Yifan Wang; Van-Meersbergen, C.; Heinen, S.) \|\| Integrated Analog Circuits, Sommerfeldstrasse 24, RWTH Aachen, Germany (Groh, H.-W.)
Abstract	The focus of this work is to provide a efficient modeling approach for the functional verification of complex analog frequency synthesizers. The event driven analog modeling approach uses the double precision data type wreal (supported by VerilogAMS), that enables analog accuracy in the digital simulation domain. It is therefore possible to separate high frequency signal paths in the frequency synthesizers from the analog domain, in order to archive higher simulation efficiency for fast verification purposes. The modeling approach and an investigation of the necessary accuracy requirements for the verification including phase noise performances of the analog frequency synthesizers is presented. The proposed approach is demonstrated on baseof a sub micron CMOS Fractional-N frequency synthesizer and compared with different traditional modeling approaches, like phase model and pure digital model. The paper concludes with a proposal of a verification approach for RF mixed signal systems.
Starting Page	25
Ending Page	30
File Size	607792
Page Count	6
File Format	PDF
ISBN	9781424453580
DOI	10.1109/BMAS.2009.5338892
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-09-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase locked loops Frequency synthesizers Semiconductor device modeling Analog circuits Phase noise Radio frequency Discrete event simulation Hardware design languages Testing Performance analysis accuracy requirements Modeling VerilogAMS wreal verification phase noise
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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