NDLI: Data-mining synthesised schedulers for hard real-time systems

Content Provider	IEEE Xplore Digital Library
Author	Kloukinas, C.
Copyright Year	2004
Description	Author affiliation: VERIMAG, Gieres (Kloukinas, C.)
Abstract	The analysis of hard real-time systems, traditionally performed using RMA/PCP or simulation, is nowadays also studied as a scheduler synthesis problem, where one automatically constructs a scheduler which can guarantee avoidance of deadlock and deadline-miss system states. Even though this approach has the potential for a finer control of a hard real-time system, using fewer resources and easily adapting to further quality aspects (memory/energy consumption, jitter minimisation, etc.), synthesised schedulers are usually extremely large and difficult to understand. Their big size is a consequence of their inherent precision, since they attempt to describe exactly the frontier among the safe and unsafe system states. It nevertheless hinders their application in practise, since it is extremely difficult to validate them or to use them for better understanding the behaviour of the system. In this paper, we show how one can adapt data-mining techniques to decrease the size of a synthesised scheduler and force its inherent structure to appear, thus giving the system designer a wealth of additional information for understanding and optimising the scheduler and the underlying system. We present, in particular, how it can be used for obtaining hints for a good task distribution to different processing units, for optimising the scheduler itself (sometimes even removing it altogether in a safe manner) and obtaining both per-task and per-system views of the schedulability of the system
Starting Page	14
Ending Page	23
File Size	350444
Page Count	10
File Format	PDF
ISBN	0769521312
ISSN	19384300
DOI	10.1109/ASE.2004.1342720
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-09-24
Publisher Place	Austria
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Real time systems Processor scheduling Performance analysis System recovery Computational modeling Analytical models Control system synthesis Energy consumption Jitter Software engineering
Content Type	Text
Resource Type	Article

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