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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Gunnam, K. Gwan Choi Yeary, M. |
| Copyright Year | 2004 |
| Description | Author affiliation: Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA (Gunnam, K.; Gwan Choi) |
| Abstract | Recent research efforts based on a joint code-decoder design methodology have shown that it is possible to construct structured LDPC (low density parity check) codes without any performance degradation. An interesting new data independence property between the two classes of messages viz. check to bit and bit to check, involved in decoding, is observed. This property is a result of the specific structuring of the parity check matrix. By exploiting this property, we propose an architecture in which the computation of messages is synchronized such that each class of message is consumed immediately by the computational unit for another class of message. The internal memory of the check to bit units is increased in tune with the storage requirement of the check to bit messages. The separate memories for check to bit and bit to check messages are eliminated. This approach has memory savings of 75% and reduces the overall memory accesses by 66%. |
| File Size | 259221 |
| File Format | |
| ISBN | 0780384849 |
| ISSN | 15206149 |
| DOI | 10.1109/ICASSP.2004.1327075 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2004-05-17 |
| Publisher Place | Canada |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Parity check codes Degradation Filling Turbo codes Sparse matrices Iterative decoding Scheduling Equations Design methodology Computer architecture |
| Content Type | Text |
| Resource Type | Article |
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