NDLI: A practical approach to DSM repeater insertion: satisfying delay constraints while minimizing area and power

Content Provider	IEEE Xplore Digital Library
Author	Nalamalpu, A. Burleson, W.
Copyright Year	2001
Description	Author affiliation: Intel Corp., Hillsboro, OR, USA (Nalamalpu, A.)
Abstract	Repeaters are now widely used to increase the performance of long on-chip interconnections in CMOS VLSI. Significantly high power consumption and area overhead due to optimal repeater insertion will soon be a bigger problem with the number of on-chip repeaters projecting to reach 700,000 in a 70 nm CMOS process. In this paper, we look at devising a methodology for minimizing power and area overhead of repeaters while meeting the target performance goals of on-chip interconnect lines. We integrate area and power overhead constraints along with delay into a repeater design methodology. We present a mathematical treatment for finding the number of repeaters and their sizes required for minimizing area and power overhead while meeting a given delay target. These expressions can easily be integrated into a repeater design methodology and CAD tool for interconnect planning. Our model is based on the Alpha-power law governing the MOSFET model to account for the short-channel effects and resistive loads that arise in deep sub-micron technologies. Results in 0.16 /spl mu/m, CMOS technology show that significant, reduction in area and power, of repeaters can be obtained by using the above design methodology.
Sponsorship	IEEE Circuits and Syst. Soc
Starting Page	152
Ending Page	156
File Size	513318
Page Count	5
File Format	PDF
ISBN	0780367413
DOI	10.1109/ASIC.2001.954689
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-09-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Repeaters Delay Design methodology CMOS technology Semiconductor device modeling Very large scale integration Energy consumption CMOS process Design automation MOSFET circuits
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in