NDLI: Automatic Verilog code generation of an 8-bit RISC micro-controller

Content Provider	IEEE Xplore Digital Library
Author	Yun-Tai Husueh Wen-Chung Chang Jui-Min Lai
Copyright Year	2002
Description	Author affiliation: Southern Taiwan Univ. of Technol., Tainan, Taiwan (Yun-Tai Husueh; Wen-Chung Chang; Jui-Min Lai)
Abstract	In this paper, we describe a design method, which can automatically generate Verilog code for an 8-bit RISC microcontroller with a user-defined instruction set. With this method, one can shorten the development time, increase the efficiency of Verilog coding, and decrease the man-hour requirement. Most of all, even those who do not have the knowledge and techniques of a Verilog coding for a RISC microcontroller are able to design a microcontroller through this method. First of all, classify the instruction set of the microcontroller to be designed, into file register and literal operation, bit file register operation, control operation, and branch operation. Then provide four stage pipeline (fetch, decode, execute and write) control signals for the microcontroller. Finally, use C/C++ language to generate the Verilog code. Finally some manually fine tune of the design is still required during pre/post simulation of the Verilog code.
Starting Page	327
Ending Page	330
File Size	247493
Page Count	4
File Format	PDF
ISBN	0780373634
DOI	10.1109/APASIC.2002.1031598
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-08-08
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware design languages Reduced instruction set computing Design methodology Databases Automatic control Pipelines Decoding Algorithms Automatic generation control Debugging
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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