NDLI: An efficient approach to low cost sequential circuit testing in a BIST environment

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An efficient approach to low cost sequential circuit testing in a BIST environment

Content Provider	IEEE Xplore Digital Library
Author	Chen, C.-I.H. O'Bleness, R.F. Yuen, J.T. Chia-Lin Chan
Copyright Year	1994
Description	Author affiliation: Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA (Chen, C.-I.H.; O'Bleness, R.F.; Yuen, J.T.; Chia-Lin Chan)
Abstract	This paper introduces a Built-In Self-Test (BIST) design methodology that can sequentially test large VLSI circuits with very high fault coverage. The proposed techniques, Circular Built-In Self-Test (CBIST) and CBIST with pseudo-partial scan (PP-SCAN), are modeled after the principles of the Circular Self-Test Path. The basis of this method is to trade a minimal increase in hardware overhead for a large increase in fault coverage. It will be shown that this technique yields a much higher fault coverage with reasonable time and test vector length when compared to existing sequential test methods.<>
Starting Page	403
Ending Page	406
File Size	437742
Page Count	4
File Format	PDF
ISBN	0780320204
DOI	10.1109/ASIC.1994.404533
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-09-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Costs Sequential circuits Sequential analysis Built-in self-test Circuit faults Design methodology Automatic testing Very large scale integration Hardware
Content Type	Text
Resource Type	Article

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