NDLI: Modeling Load Variations with Artificial Neural Networks to Improve On-Wafer OSLT Calibrations

Content Provider	IEEE Xplore Digital Library
Author	Jargon, Jeffrey A. Kirby, Pete Gupta, K. C. Dunleavy, Lawrence Weller, Tom
Copyright Year	2000
Description	Author affiliation: National Institute of Standards and Technology, RF Electronics Group, 325 Broadway, Boulder, CO 80303, e-mail: jargon@boulder.nist.gov (Jargon, Jeffrey A.) \|\| Wireless and Microwave (WAMI) Program, University of South Florida, Tampa, FL 33620 (Kirby, Pete; Dunleavy, Lawrence; Weller, Tom) \|\| Center for Advanced Manufacturing and Packaging of Microwave, Optical, and Digital Electronics (CAMPmode), University of Colorado at Boulder, Boulder, CO 80309 (Gupta, K. C.)
Abstract	We demonstrate that on-wafer open-short-load-thru (OSLT) calibrations of vector network analyzers can be improved by applying artificial neural networks (ANNs) to model the correlation between DC resistance and RF variations in load terminations. The ANNs are trained with measurement data obtained from a benchmark multiline thru-reflect-line (TRL) calibration. The open, short, and thru standards do not vary significantly from wafer to wafer, so we also model these standards using ANNs trained with calibrated measurement data chosen from an arbitrary wafer. We assess the accuracy of five OSLT calibrations with varying load terminations using the ANN-modeled standards, and find that they compare favorably (a difference of less than 0.04 in magnitude at most frequencies) to the benchmark multiline TRL calibration over a 66 GHz bandwidth. We demonstrate that ANN models offer a number of advantages over using calibrated measurement files or equivalent circuit models, including ease of use, reduced calibration times, and compactness.
Starting Page	1
Ending Page	13
File Size	186936
Page Count	13
File Format	PDF
ISBN	0780356861
DOI	10.1109/ARFTG.2000.327430
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-11-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Load modeling Load management Artificial neural networks Calibration Semiconductor device modeling Electrical resistance measurement Measurement standards Radio frequency Bandwidth Equivalent circuits
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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